Abstract: An input/output interface unit includes a plurality of ports connected to different external units, and adds predetermined identification information unique to each of the ports to an interrupt request received from each of the external units via the ports. An interrupt control unit stores information on the interrupt request received by the input/output interface unit in a vector storage unit based on the identification information. Each of cores executes a process corresponding to the interrupt request stored in the vector storage unit based on the identification information.

Abstract: A plurality of barrier blades, a barrier blade identification information storage unit, and a barrier blade identification information selection unit are provided. The plurality of barrier blades synchronize, using a synchronization address set for a plurality of arithmetic processing units, the plurality of arithmetic processing units. The barrier blade identification information storage unit holds barrier blade identification information to identify the barrier blade corresponding to synchronization address identification information to identify the synchronization address, for each of the plurality of arithmetic processing units. When synchronization address identification information is input, the barrier blade identification information selection unit selects and outputs barrier blade identification information corresponding to the input synchronization address identification information, among barrier blade identification information held by the barrier blade identification information storage unit.

Abstract: A cache memory control device includes: a determination unit for determining whether or not a command provided from, for example, each core is to access cache memory during the execution of the command; and a path switch unit for putting a command determined as accessing the cache memory in pipeline processing, and outputting a command determined as not accessing the cache memory directly to an external unit without putting the command in the pipeline processing.

Abstract: With a view to reducing the congestion of a pipeline for cache memory access in, for example, a multi-core system, a cache memory control device includes: a determination unit for determining whether or not a command provided from, for example, each core is to access cache memory during the execution of the command; and a path switch unit for putting a command determined as accessing the cache memory in pipeline processing, and outputting a command determined as not accessing the cache memory directly to an external unit without putting the command in the pipeline processing.

Abstract: A cache memory control circuit allowing an MIB to have information concerning an upper address section of a replace address corresponding to a move-in request and information indicating whether a replace destination is valid or not includes: a first determination section (step S41) that determines whether an index and upper address section of the request address related to the move-in request and those of the request address that is related to a preceding move-in request and has been registered in the MIB do not correspond respectively to each other, a third determination section (step S42) that determines whether an index and upper address section in the address related to the move-in request and those in the replace address that is related to the preceding move-in request and has been registered in the MIB do not correspond respectively to each other; and a tag search section (step S43) that continues the processing for the move-in request in the case where an affirmative result has been obtained both in th

Abstract: A cross call send control unit (XCSC) of an external interface unit of each CPU controls cross call transmission issued by a CPU core unit to another CPU. The XCSC has a register for keeping the processing state of the processing relating to the cross call directly associated with an issue history of the cross call for each entry.

Abstract: A cache memory control circuit allowing an MIB to have information concerning an upper address section of a replace address corresponding to a move-in request and information indicating whether a replace destination is valid or not includes: a first determination section (step S41) that determines whether an index and upper address section of the request address related to the move-in request and those of the request address that is related to a preceding move-in request and has been registered in the MIB do not correspond respectively to each other, a third determination section (step S42) that determines whether an index and upper address section in the address related to the move-in request and those in the replace address that is related to the preceding move-in request and has been registered in the MIB do not correspond respectively to each other; and a tag search section (step S43) that continues the processing for the move-in request in the case where an affirmative result has been obtained both in th