Patents by Inventor Koki KISHIMOTO

Koki KISHIMOTO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12684150
    Abstract: A mesh decoding device 200 according to the present invention includes a circuit, wherein the circuit: subdivides a base mesh and output an initial subdivided mesh; calculates a normal for each vertex forming the initial subdivided mesh; and adjusts a subdivided mesh by dividing a subdivided face after moving a position of the vertex forming a face of the initial subdivided mesh.
    Type: Grant
    Filed: February 24, 2025
    Date of Patent: July 14, 2026
    Assignee: KDDI CORPORATION
    Inventors: Koki Kishimoto, Kei Kawamura
  • Publication number: 20260187852
    Abstract: A mesh decoding device 200 according to the present invention includes: an atlas data decoding unit 207 decodes an atlas bit stream to generate and output control information; a base mesh decoding unit 202 decodes the control information and a base mesh bit stream to generate and output a base mesh; a subdivision unit 203 outputs a subdivision mesh and a subdivision vertex normal line using the control information and the base mesh as inputs; a mesh decoding unit 204 generates a decoded mesh using the control information, a displacement, the subdivision mesh, and the subdivision vertex normal line as inputs; and a boundary correction unit 208 corrects a sub-mesh boundary for the decoded mesh and output a boundary corrected decoded mesh.
    Type: Application
    Filed: February 26, 2026
    Publication date: July 2, 2026
    Applicant: KDDI CORPORATION
    Inventors: Koki KISHIMOTO, Kei KAWAMURA
  • Publication number: 20260181171
    Abstract: A mesh decoding device 200 according to the present invention includes: an atlas data decoding unit 207 configured to decode a syntax defining a maximum value of the number of iterations of subdivision, wherein the syntax decoded by the atlas data decoding unit 207 has a value of 15 or less.
    Type: Application
    Filed: December 16, 2025
    Publication date: June 25, 2026
    Applicant: KDDI CORPORATION
    Inventors: Emi MYOUDOU, Jiangfen XU, Koki KISHIMOTO, Kei KAWAMURA
  • Publication number: 20260156284
    Abstract: A mesh decoding device (200) according to the present invention includes: an atlas data decoding unit (207) configured to decode an atlas bit stream to generate and output control information. According to the present invention, it is possible to efficiently compress a displacement amount.
    Type: Application
    Filed: December 16, 2025
    Publication date: June 4, 2026
    Applicant: KDDI CORPORATION
    Inventors: Koki KISHIMOTO, Kei KAWAMURA
  • Publication number: 20260122272
    Abstract: A mesh decoding device (200) according to the present invention includes: an atlas data decoding unit (207) that decodes an atlas bit stream to generate and output first control information; a base mesh decoding unit (202) that decodes a base mesh bit stream to generate and output second control information and a base mesh; a subdivision unit (203) that outputs a subdivision mesh and a subdivision vertex normal using the first control information, the second control information, and the base mesh as inputs; and a mesh decoding unit (204) that generates a decoded mesh using the first control information, the displacement amount, the subdivision mesh, and the subdivision vertex normal as inputs.
    Type: Application
    Filed: December 10, 2025
    Publication date: April 30, 2026
    Applicant: KDDI CORPORATION
    Inventors: Koki KISHIMOTO, Kei KAWAMURA
  • Publication number: 20250220232
    Abstract: A mesh decoding device 200 includes a circuit that: outputs a base mesh, outputs an intra prediction residual, and decodes a displacement by performing intra prediction of a displacement of a subdivided vertex based on the outputted base mesh to calculate an intra prediction value, and adding the calculated intra prediction value and the outputted intra prediction residual.
    Type: Application
    Filed: February 24, 2025
    Publication date: July 3, 2025
    Applicant: KDDI CORPORATION
    Inventors: Koki KISHIMOTO, Kei KAWAMURA
  • Publication number: 20250218047
    Abstract: The present invention enables setting of a decoding method according to characteristics of a mesh in a patch and can reduce the number of bits of a displacement. A mesh decoding device 200 according to the present invention includes a circuit, wherein the circuit: decodes an atlas bit stream and output patch information and frame information; changes a subdivision method based on the patch information and the frame information; and changes an inverse quantization method based on the patch information.
    Type: Application
    Filed: February 24, 2025
    Publication date: July 3, 2025
    Applicant: KDDI CORPORATION
    Inventors: Koki KISHIMOTO, Kei KAWAMURA
  • Publication number: 20250220211
    Abstract: A mesh decoding device 200 according to the present invention includes a circuit, wherein the circuit: subdivides a base mesh and output an initial subdivided mesh; calculates a normal for each vertex forming the initial subdivided mesh; and adjusts a subdivided mesh by dividing a subdivided face after moving a position of the vertex forming a face of the initial subdivided mesh.
    Type: Application
    Filed: February 24, 2025
    Publication date: July 3, 2025
    Applicant: KDDI CORPORATION
    Inventors: Koki KISHIMOTO, Kei KAWAMURA
  • Publication number: 20240194613
    Abstract: A power semiconductor according to the present disclosed technology is a case-type power semiconductor device, in which a case is formed by mixing a heavy element material and a conductive material with a material having high processability, the conductive material is not a light metal, and the electric resistance of the case is 1.0 E5 to 1.0 E11 [?]. In addition, the power semiconductor according to the present disclosed technology is a transfer mold-type power semiconductor device, and includes a transfer mold-type sealing resin including a sealing resin containing a heavy element material and a sealing resin containing a conductive material, in which the conductive material of the sealing resin containing a conductive material is not a light metal.
    Type: Application
    Filed: April 2, 2021
    Publication date: June 13, 2024
    Applicant: Mitsubishi Electric Corporation
    Inventors: Hirotaku ISHIKAWA, Koki KISHIMOTO, Kazutake KADOWAKI, Kunihiko TAJIRI, Yoshitaka MIYAJI, Hiroki SHIOTA, Yasutomo OTAKE