Abstract: A scheduling unit (110) of a circuit design assistance device (100) acquires a high-level description (61) including a plurality of external memory accesses from a plurality of modules, required circuit performance (63), and external memory information (64). The scheduling unit (110) identifies external memory accesses that operate in parallel in a circuit, and determines an issue order (72) of the external memory accesses that operate in parallel so as to satisfy the required circuit performance (63). A circuit generation unit (120) of the circuit design assistance device (100) generates a circuit description (65) of an external memory access circuit including a scheduler circuit that issues the external memory accesses that operate in parallel in the issue order (72).

Abstract: An input-output data collector collects, from a programmable logic controller, input-output data representing a log for a device in a program predetermined as a logging target program of one or more programs executable by the programmable logic controller. An input-output data generator generates, when a debugging target program is determined not to be included in the predetermined program, input-output data representing a log for a device in the debugging target program by executing a simulation program simulating an operation of the programmable logic controller.

Abstract: An input-output data collector collects, from a programmable logic controller, input-output data representing a log for a device in a program predetermined as a logging target program of one or more programs executable by the programmable logic controller. An input-output data generator generates, when a debugging target program is determined not to be included in the predetermined program, input-output data representing a log for a device in the debugging target program by executing a simulation program simulating an operation of the programmable logic controller.

Abstract: An acceptance unit accepts architecture information, a processing program, and a constraint condition. An objective function generation unit generates an objective function about an evaluation item of each constituent element indicated by the architecture information. An optimization unit solves an optimization problem of the objective function once or more to obtain one partitioning solution or more about the one constituent element or more and the one subroutine or more. A margin degree calculation unit calculates, concerning an evaluation item of each constituent element, a margin degree of each constituent element based on the one partitioning solution or more and the constraint condition. A change determination unit determines whether or not each constituent element needs to be changed, based on the margin degree of the constituent element. A change unit changes the architecture information about each constituent element that needs to be changed.

Abstract: In an architecture selection device, an evaluation unit evaluates performance of each of candidates for a combination of processing components to be integrated into a system to be designed. An aggregation unit aggregates costs of each of candidates for a combination of hardware components to be integrated into the system to be designed. A first selection unit and a second selection unit select one combination of the hardware components, as architecture of the system to be designed, from among the candidates for the combination of the hardware components to be integrated into the system to be designed. The combination of the hardware components that is to be selected is a combination of the hardware components which includes a combination of the processing components having the performance evaluated by the evaluation unit satisfying a constraint condition on the performance and whose costs aggregated by the aggregation unit satisfy a constraint condition on the costs.

Abstract: A processing dividing unit (130) extracts, from a function model (210) including one or more loop processes, each of the one or more loop processes. A parameter extracting unit (140) determines the characteristics of each extracted loop process. A performance calculation basic formula selecting unit (150) selects, for each loop process, from a plurality of processing time calculation procedures for calculating a processing time, a processing time calculation procedure for calculating a processing time of each loop process, based on the characteristics of each loop process and the architecture of computational resources executing the function model (210). A performance estimating unit (160) calculates a processing time of each loop process by using a corresponding processing time calculation procedure selected by the performance calculation basic formula selecting unit (150).

Abstract: An analysis unit divides hierarchized program code into a plurality of program elements in accordance with a predetermined division condition, analyzes each of the plurality of program elements, and extracts an attribute of each program element and a hierarchy of the plurality of program elements. A functional module extraction unit performs machine learning on the basis of the attribute of each program element and the hierarchy of the plurality of program elements extracted by the analysis unit and groups the plurality of program elements into a plurality of groups.

Abstract: A specification editing unit edits a hardware specification file in order to replace a plurality of arrays used in a plurality of processes with a shared array. If a post-edit hardware specification file does not satisfy constraint, a specification transforming unit transforms the hardware specification file so that the plurality of processes are executed in a parallel manner. An architecture generating unit generates an architecture file expressing an architecture of an SoC (System On Chip) having hardware corresponding to the hardware specification file.

Abstract: A specification editing unit edits a hardware specification file in order to replace a plurality of arrays used in a plurality of processes with a shared array. If a post-edit hardware specification file does not satisfy constraint, a specification transforming unit transforms the hardware specification file so that the plurality of processes are executed in a parallel manner. An architecture generating unit generates an architecture file expressing an architecture of an SoC (System On Chip) having hardware corresponding to the hardware specification file.