Patents by Inventor Koki Yano

Koki Yano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11769840
    Abstract: A schottky barrier diode element having a silicon (Si) substrate, an oxide semiconductor layer and a schottky electrode layer, wherein the oxide semiconductor layer includes a polycrystalline and/or amorphous oxide semiconductor having a band gap of 3.0 eV or more and 5.6 eV or less.
    Type: Grant
    Filed: May 25, 2017
    Date of Patent: September 26, 2023
    Assignee: IDEMITSU KOSAN CO., LTD.
    Inventors: Shigekazu Tomai, Masatoshi Shibata, Emi Kawashima, Koki Yano, Hiromi Hayasaka
  • Publication number: 20210020784
    Abstract: A field effect transistor including: a substrate, and at least gate electrode, a gate insulating film, a semiconductor layer, a protective layer for the semiconductor layer, a source electrode and a drain electrode provided on the substrate, wherein the source electrode and the drain electrode are connected with the semiconductor layer therebetween, the gate insulating film is between the gate electrode and the semiconductor layer, the protective layer is on at least one surface of the semiconductor layer, the semiconductor layer includes an oxide containing In atoms, Sn atoms and Zn atoms, the atomic composition ratio of Zn/(In+Sn+Zn) is 25 atom % or more and 75 atom % or less, and the atomic composition ratio of Sn/(In+Sn+Zn) is less than 50 atom %.
    Type: Application
    Filed: September 24, 2020
    Publication date: January 21, 2021
    Applicant: IDEMITSU KOSAN CO., LTD.
    Inventors: Koki YANO, Hirokazu KAWASHIMA, Kazuyoshi INOUE
  • Patent number: 10833201
    Abstract: A field effect transistor including: a substrate, and at least gate electrode, a gate insulating film, a semiconductor layer, a protective layer for the semiconductor layer, a source electrode and a drain electrode provided on the substrate, wherein the source electrode and the drain electrode are connected with the semiconductor layer therebetween, the gate insulating film is between the gate electrode and the semiconductor layer, the protective layer is on at least one surface of the semiconductor layer, the semiconductor layer includes an oxide containing In atoms, Sn atoms and Zn atoms, the atomic composition ratio of Zn/(In+Sn+Zn) is 25 atom % or more and 75 atom % or less, and the atomic composition ratio of Sn/(In+Sn+Zn) is less than 50 atom %.
    Type: Grant
    Filed: March 21, 2016
    Date of Patent: November 10, 2020
    Assignee: IDEMITSU KOSAN CO., LTD.
    Inventors: Koki Yano, Hirokazu Kawashima, Kazuyoshi Inoue
  • Patent number: 10644163
    Abstract: A field effect transistor including: a substrate, and at least gate electrode, a gate insulating film, a semiconductor layer, a protective layer for the semiconductor layer, a source electrode and a drain electrode provided on the substrate, wherein the source electrode and the drain electrode are connected with the semiconductor layer therebetween, the gate insulating film is between the gate electrode and the semiconductor layer, the protective layer is on at least one surface of the semiconductor layer, the semiconductor layer includes an oxide containing In atoms, Sn atoms and Zn atoms, the atomic composition ratio of Zn/(In+Sn+Zn) is 25 atom % or more and 75 atom % or less, and the atomic composition ratio of Sn/(In+Sn+Zn) is less than 50 atom %.
    Type: Grant
    Filed: August 26, 2009
    Date of Patent: May 5, 2020
    Assignee: IDEMITSU KOSAN CO., LTD.
    Inventors: Koki Yano, Hirokazu Kawashima, Kazuyoshi Inoue
  • Publication number: 20170263786
    Abstract: A schottky barrier diode element having a silicon (Si) substrate, an oxide semiconductor layer and a schottky electrode layer, wherein the oxide semiconductor layer includes a polycrystalline and/or amorphous oxide semiconductor having a band gap of 3.0 eV or more and 5.6 eV or less.
    Type: Application
    Filed: May 25, 2017
    Publication date: September 14, 2017
    Applicant: IDEMITSU KOSAN CO., LTD.
    Inventors: Shigekazu TOMAI, Masatoshi SHIBATA, Emi KAWASHIMA, Koki YANO, Hiromi HAYASAKA
  • Patent number: 9691910
    Abstract: A schottky barrier diode element having a silicon (Si) substrate, an oxide semiconductor layer and a schottky electrode layer, wherein the oxide semiconductor layer includes a polycrystalline and/or amorphous oxide semiconductor having a band gap of 3.0 eV or more and 5.6 eV or less.
    Type: Grant
    Filed: August 8, 2014
    Date of Patent: June 27, 2017
    Assignee: IDEMITSU KOSAN CO., LTD.
    Inventors: Shigekazu Tomai, Masatoshi Shibata, Emi Kawashima, Koki Yano, Hiromi Hayasaka
  • Publication number: 20170141240
    Abstract: A Schottky barrier diode element includes an n-type or p-type silicon (Si) substrate, an oxide semiconductor layer, and a Schottky electrode layer, the oxide semiconductor layer including either or both of a polycrystalline oxide that includes gallium (Ga) as the main component and an amorphous oxide that includes gallium (Ga) as the main component.
    Type: Application
    Filed: December 28, 2016
    Publication date: May 18, 2017
    Applicant: IDEMITSU KOSAN CO., LTD.
    Inventors: Shigekazu TOMAI, Masatoshi SHIBATA, Emi KAWASHIMA, Koki YANO, Hiromi HAYASAKA
  • Patent number: 9570631
    Abstract: A Schottky barrier diode element includes an n-type or p-type silicon (Si) substrate, an oxide semiconductor layer, and a Schottky electrode layer, the oxide semiconductor layer including either or both of a polycrystalline oxide that includes gallium (Ga) as the main component and an amorphous oxide that includes gallium (Ga) as the main component.
    Type: Grant
    Filed: August 8, 2014
    Date of Patent: February 14, 2017
    Assignee: IDEMITSU KOSAN CO., LTD.
    Inventors: Shigekazu Tomai, Masatoshi Shibata, Emi Kawashima, Koki Yano, Hiromi Hayasaka
  • Publication number: 20160211386
    Abstract: A Schottky barrier diode element includes an n-type or p-type silicon (Si) substrate, an oxide semiconductor layer, and a Schottky electrode layer, the oxide semiconductor layer including either or both of a polycrystalline oxide that includes gallium (Ga) as the main component and an amorphous oxide that includes gallium (Ga) as the main component.
    Type: Application
    Filed: August 8, 2014
    Publication date: July 21, 2016
    Applicant: IDEMITSU KOSAN CO., LTD.
    Inventors: Shigekazu TOMAI, Masatoshi SHIBATA, Emi KAWASHIMA, Koki YANO, Hiromi HAYASAKA
  • Publication number: 20160201187
    Abstract: A field effect transistor including: a substrate, and at least gate electrode, a gate insulating film, a semiconductor layer, a protective layer for the semiconductor layer, a source electrode and a drain electrode provided on the substrate, wherein the source electrode and the drain electrode are connected with the semiconductor layer therebetween, the gate insulating film is between the gate electrode and the semiconductor layer, the protective layer is on at least one surface of the semiconductor layer, the semiconductor layer includes an oxide containing In atoms, Sn atoms and Zn atoms, the atomic composition ratio of Zn/(In+Sn+Zn) is 25 atom % or more and 75 atom % or less, and the atomic composition ratio of Sn/(In+Sn+Zn) is less than 50 atom %.
    Type: Application
    Filed: March 21, 2016
    Publication date: July 14, 2016
    Applicant: IDEMITSU KOSAN CO., LTD.
    Inventors: Koki YANO, Hirokazu KAWASHIMA, Kazuyoshi INOUE
  • Publication number: 20160197202
    Abstract: A schottky barrier diode element having a silicon (Si) substrate, an oxide semiconductor layer and a schottky electrode layer, wherein the oxide semiconductor layer includes a polycrystalline and/or amorphous oxide semiconductor having a band gap of 3.0 eV or more and 5.6 eV or less.
    Type: Application
    Filed: August 8, 2014
    Publication date: July 7, 2016
    Applicant: IDEMITSU KOSAN CO., LTD.
    Inventors: Shigekazu TOMAI, Masatoshi SHIBATA, Emi KAWASHIMA, Koki YANO, Hiromi HAYASAKA
  • Patent number: 9269573
    Abstract: To provide a thin film transistor having an indium oxide-based semiconductor film which allows only a thin metal film on the semiconductor film to be selectively etched. A thin film transistor having a crystalline indium oxide semiconductor film which is composed mainly of indium oxide and contains a positive trivalent metal oxide.
    Type: Grant
    Filed: September 18, 2008
    Date of Patent: February 23, 2016
    Assignee: IDEMITSU KOSAN CO., LTD.
    Inventors: Kazuyoshi Inoue, Koki Yano, Shigekazu Tomai, Futoshi Utsuno, Masashi Kasami, Kenji Goto, Hirokazu Kawashima
  • Patent number: 9243318
    Abstract: A sintered body which includes at least indium oxide and gallium oxide and comprises voids each having a volume of 14000 ?m3 or more in an amount of 0.03 vol % or less.
    Type: Grant
    Filed: March 26, 2012
    Date of Patent: January 26, 2016
    Assignee: IDEMITSU KOSAN CO., LTD.
    Inventors: Shigekazu Tomai, Shigeo Matsuzaki, Koki Yano, Makoto Ando, Kazuaki Ebata, Masayuki Itose
  • Patent number: 9214519
    Abstract: A sputtering target including indium (In), tin (Sn) and zinc (Zn) and an oxide including one or more elements X selected from the following group X, the atomic ratio of the elements satisfying the following formulas (1) to (4): Group X: Mg, Si, Al, Sc, Ti, Y, Zr, Hf, Ta, La, Nd, Sm 0.10?In/(In+Sn+Zn)?0.85??(1) 0.01?Sn/(In+Sn+Zn)?0.40??(2) 0.10?Zn/(In+Sn+Zn)?0.70??(3) 0.70?In/(In+X)?0.99??(4).
    Type: Grant
    Filed: May 7, 2012
    Date of Patent: December 15, 2015
    Assignee: IDEMITSU KOSAN CO., LTD.
    Inventors: Masayuki Itose, Mami Nishimura, Misa Sunagawa, Masashi Kasami, Koki Yano
  • Patent number: 9209257
    Abstract: An oxide sintered body includes indium oxide and gallium solid-solved therein, the oxide sintered body having an atomic ratio “Ga/(Ga+In)” of 0.001 to 0.12, containing indium and gallium in an amount of 80 atom % or more based on total metal atoms, and having an In2O3 bixbyite structure.
    Type: Grant
    Filed: November 20, 2013
    Date of Patent: December 8, 2015
    Assignee: Idemitsu Kosan Co., Ltd.
    Inventors: Futoshi Utsuno, Kazuyoshi Inoue, Hirokazu Kawashima, Masashi Kasami, Koki Yano, Kota Terai
  • Patent number: 9202603
    Abstract: A sputtering target including indium, tin, zinc and oxygen, and including a hexagonal layered compound, a spinel structure compound and a bixbyite structure compound.
    Type: Grant
    Filed: December 12, 2012
    Date of Patent: December 1, 2015
    Assignee: Idemitsu Kosan Co., Ltd.
    Inventors: Koki Yano, Kazuyoshi Inoue, Nobuo Tanaka
  • Patent number: 9153438
    Abstract: An oxide sintered body including an oxide of indium and aluminum and having an atomic ratio Al/(Al+In) of 0.01 to 0.08.
    Type: Grant
    Filed: May 24, 2011
    Date of Patent: October 6, 2015
    Assignee: IDEMITSU KOSAN CO., LTD.
    Inventors: Kazuaki Ebata, Shigekazu Tomai, Koki Yano, Kazuyoshi Inoue
  • Patent number: 9136338
    Abstract: Disclosed is a sputtering target having a good appearance, which is free from white spots on the surface. The sputtering target is characterized by being composed of an oxide sintered body containing two or more kinds of homologous crystal structures.
    Type: Grant
    Filed: April 25, 2013
    Date of Patent: September 15, 2015
    Assignee: IDEMITSU KOSAN CO., LTD.
    Inventors: Koki Yano, Hirokazu Kawashima, Kazuyoshi Inoue
  • Patent number: 9054196
    Abstract: A thin film transistor including an active layer, and has a field-effect mobility of 25 cm2/Vs or more, the active layer being formed of an oxide that includes In, Ga, and Zn in an atomic ratio that falls within the following region 1, region 2, or region 3, the region 1 being defined by 0.58?In/(In+Ga+Zn)?0.68 and 0.15<Ga/(In+Ga+Zn)?0.29, the region 2 being defined by 0.45?In/(In+Ga+Zn)<0.58 and 0.09?Ga/(In+Ga+Zn)<0.20, and the region 3 being defined by 0.45?In/(In+Ga+Zn)<0.58 and 0.20?Ga/(In+Ga+Zn)?0.27.
    Type: Grant
    Filed: May 1, 2012
    Date of Patent: June 9, 2015
    Assignee: IDEMITSU KOSAN CO., LTD.
    Inventors: Masayuki Itose, Mami Nishimura, Hirokazu Kawashima, Misa Sunagawa, Masashi Kasami, Koki Yano
  • Patent number: 9039944
    Abstract: A sputtering target including a sintered body including In, Ga and Mg, the sintered body including one or more compounds selected from a compound represented by In2O3, a compound represented by In(GaMg)O4, a compound represented by Ga2MgO4 and a compound represented by In2MgO4, and having an atomic ratio In/(In+Ga+Mg) of 0.5 or more and 0.9999 or less and an atomic ratio (Ga+Mg)/(In+Ga+Mg) of 0.0001 or more and 0.5 or less.
    Type: Grant
    Filed: June 28, 2012
    Date of Patent: May 26, 2015
    Assignee: IDEMITSU KOSAN CO., LTD.
    Inventors: Kazuaki Ebata, Shigekazu Tomai, Kota Terai, Shigeo Matsuzaki, Koki Yano