Abstract: A BiCMOS process which provides both isolated and vertical NPN and PNP transistors with better performance characteristics and fewer additional steps than the prior art. The additional steps consist of masked implants with no changes in the thermal steps of the CMOS process. An N-well to contain the vertical PNP transistor is formed during the same step that the NPN vertical transistor collector is formed. The N base of the PNP transistor is formed by implanting an N type material. A P type material is implanted at a high energy of at least 300 keV (150 for doubly ionized Boron) to form a collector of the PNP transistor. A P region is then formed as an emitter of PNP transistor. The high energy P implant gives a peak at approximately 0.8 .mu.m below the surface to form the equivalent of a buried layer (without growing an epitaxial layer after a P implant to form a buried layer as in the prior art).