Abstract: Pattern transfer from a resist to an underlying layer is accomplished by etching the underlying layer in a plasma comprising hydrogen bromide and oxygen. Accuracy of pattern transfer is obtained by using first and second materials underneath the resist. The first and second materials may be, e.g., polysilicon and a photoresist. Etching of the resist is performed under conditions designed to minimize changes in the horizontal dimensions.

Abstract: A method for forming an integrated circuit with a planarized dielectric is disclosed. Runners and gates are covered with a protective dielectric layer. Then a conventional dielectric is deposited and planarized over the entire circuit surface. When windows are opened to runners and to source/drain regions, the protective dielectric helps to slow the etch process over the runner, thus protecting the runner from damage during the extra time required for the etch process to reach the source or drain.

Abstract: An integrated circuit is made by a technique that provides a planar dielectric over gate, source, and drain regions without over-etching of the gate contact region, In the inventive process, the contact windows are etched in the conformal dielectric prior to the planarization step, so that the etch thickness is the same for the gate as for the source/drain windows. Then, a sacrificial planarizing polymer (e.g., a photoresist) is deposited to cover the conformal dielectric and fill the etched windows. Finally, a planarizing etch-back is performed, and the polymer is removed from the contact windows. A planarized dielectric is achieved without excessive etching of the gate windows.