Abstract: A devices and method for parsing a data stream comprises a parser stack configured to store one or more parsing symbols, each parsing symbol representing a different state of data stream parsing, a table interface configured to retrieve one or more production rules from a production rule table according to the parsing symbols, and a state machine configured to control the parsing of a data stream according to the retrieved production rules.

Abstract: A device comprises a plurality of interface circuits configured for communicating between a semantic processing unit and a memory and a selection circuit for selecting an interface circuit allocated to a semantic processing unit for processing a data operation request in the memory.

Abstract: A device performs lookup functions for a semantic processing unit. The device comprises a plurality of interface circuits for receiving data operation requests from the semantic processing unit. The device comprises a buffer for allocating an interface circuit to a semantic processing unit having a data operation request. A selection circuit, coupled between the plurality of interface circuits and a memory unit, selects an allocated circuit for accessing the memory unit to process the data operation request.

Abstract: A system and method for parsing a data stream comprises a production rule table populated with production rules, a parser table populated with production rule codes that correspond to production rules within the production rule table, and a direct execution parser to identify production rule codes in the parser table and to retrieve production rules from the production rule table according to the identified production rule codes, the direct execution parser is operable to parse a data stream according to the retrieved production rules.

Abstract: A device has an input port to allow the device to receive data. The device also has a parser to parse the data in response to symbols in a parser stack, determine when a symbol is a debug non-terminal symbol, and notify the device via an interrupt. The interrupt causes the device to gather information about the state of the parser at the time of encountering the non-terminal symbol.

Abstract: A system and method comprising a direct memory access (DMA) circuit configured to directly access a memory, and a checksum adder configured to determine a checksum for data transferred between the DMA circuit and the memory.

Abstract: A system and method comprising a buffer configured to receive a data stream, a parser configured to parse the data stream from the buffer, and one or more processing units configured to co-process the data stream from the buffer responsive to the parsing by the parser, and then provide at least a portion of the processed data stream back to the buffer for additional parsing by the parser.

Abstract: A devices and method for parsing a data stream comprises a parser stack configured to store one or more parsing symbols, each parsing symbol representing a different state of data stream parsing, a table interface configured to retrieve one or more production rules from a production rule table according to the parsing symbols, and a state machine configured to control the parsing of a data stream according to the retrieved production rules.

Abstract: A device comprises a plurality of interface circuits configured for communicating between a semantic processing unit and a memory and a selection circuit for selecting an interface circuit allocated to a semantic processing unit for processing a data operation request in the memory.

Abstract: A device performs lookup functions for a semantic processing unit. The device comprises a plurality of interface circuits for receiving data operation requests from the semantic processing unit. The device comprises a buffer for allocating an interface circuit to a semantic processing unit having a data operation request. A selection circuit, coupled between the plurality of interface circuits and a memory unit, selects an allocated circuit for accessing the memory unit to process the data operation request.

Abstract: A device comprises a plurality of interface circuits for communicating between a semantic processor and a memory. Each interface circuit is configured for receiving lookup requests from the semantic processor. The device further comprises a buffer for allocating an interface circuit, if available, to the semantic processor. The allocated interface circuit is selected to access the memory for processing the lookup request.

Abstract: A system and method for parsing a data stream comprises a production rule table populated with production rules, a parser table populated with production rule codes that correspond to production rules within the production rule table, and a direct execution parser to identify production rule codes in the parser table and to retrieve production rules from the production rule table according to the identified production rule codes, the direct execution parser is operable to parse a data stream according to the retrieved production rules.

Abstract: A system and device are disclosed for operating an interface circuit. The interface circuit comprises a buffer for buffering data, a parser interface for sending at least a portion of the buffered data to a direct execution parser, and a processing interface for sending at least a portion of the buffered data to a semantic processing unit. The system comprises a plurality of input buffers for buffering received data, a direct execution parser configured to parse the data in the input buffers in response to symbols in a parser stack, and a plurality of semantic processing units each configured to perform operations on data in the different input buffers according to commands from the direct execution parser.

Abstract: A method and apparatus for randomly selecting which of a plurality of memory modules data packets are to be written to in a network packet buffer. Memory modules are coupled in parallel to effectively increase the overall memory bandwidth. In order to minimize latency, each time an incoming packet is received by the network switch, a scheduler randomly selects one of the memory modules to which that packet is to be stored upon. And because the data is randomly distributed amongst the different memory modules, read operations will be similarly random across all memory modules. This ensures minimal read latencies when reading data from the memories. Thereby, the delays are minimized.