Patents by Inventor Kon Ha
Kon Ha has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10937788Abstract: A semiconductor device includes a substrate with an active region, a plurality of conductive line structures on the substrate, an insulating layer separating the plurality of conductive line structures from the substrate, a contact plug between every two adjacent conductive line structures, an insulating spacer structure between each conductive line structure and a corresponding contact plug, a landing pad connected to each contact plug, and a landing pad insulation pattern having an asymmetrical shape based on a vertical axis of the landing pad that extends along a normal to the substrate. The landing pad insulation pattern includes a first portion overlapping the conductive line structures and a second portion overlapping the contact plug, the first and second portions being on opposite sides of the vertical axis.Type: GrantFiled: March 5, 2020Date of Patent: March 2, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Nam-Gun Kim, Sang-min Lee, Tae-Seop Choi, Kon Ha, Seung-jae Lee
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Publication number: 20200203348Abstract: A semiconductor device includes a substrate with an active region, a plurality of conductive line structures on the substrate, an insulating layer separating the plurality of conductive line structures from the substrate, a contact plug between every two adjacent conductive line structures, an insulating spacer structure between each conductive line structure and a corresponding contact plug, a landing pad connected to each contact plug, and a landing pad insulation pattern having an asymmetrical shape based on a vertical axis of the landing pad that extends along a normal to the substrate. The landing pad insulation pattern includes a first portion overlapping the conductive line structures and a second portion overlapping the contact plug, the first and second portions being on opposite sides of the vertical axis.Type: ApplicationFiled: March 5, 2020Publication date: June 25, 2020Inventors: Nam-gun KIM, Sang-min LEE, Tae-seop CHOI, Kon HA, Seung-jae LEE
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Patent number: 10622360Abstract: A semiconductor device includes a substrate with an active region, a plurality of conductive line structures on the substrate, an insulating layer separating the plurality of conductive line structures from the substrate, a contact plug between every two adjacent conductive line structures, an insulating spacer structure between each conductive line structure and a corresponding contact plug, a landing pad connected to each contact plug, and a landing pad insulation pattern having an asymmetrical shape based on a vertical axis of the landing pad that extends along a normal to the substrate. The landing pad insulation pattern includes a first portion overlapping the conductive line structures and a second portion overlapping the contact plug, the first and second portions being on opposite sides of the vertical axis.Type: GrantFiled: January 22, 2019Date of Patent: April 14, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Nam-gun Kim, Sang-min Lee, Tae-seop Choi, Kon Ha, Seung-jae Lee
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Publication number: 20190157273Abstract: A semiconductor device includes a substrate with an active region, a plurality of conductive line structures on the substrate, an insulating layer separating the plurality of conductive line structures from the substrate, a contact plug between every two adjacent conductive line structures, an insulating spacer structure between each conductive line structure and a corresponding contact plug, a landing pad connected to each contact plug, and a landing pad insulation pattern having an asymmetrical shape based on a vertical axis of the landing pad that extends along a normal to the substrate. The landing pad insulation pattern includes a first portion overlapping the conductive line structures and a second portion overlapping the contact plug, the first and second portions being on opposite sides of the vertical axis.Type: ApplicationFiled: January 22, 2019Publication date: May 23, 2019Inventors: Nam-gun KIM, Sang-min LEE, Tae-seop CHOI, Kon HA, Seung-jae LEE
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Patent number: 10290509Abstract: Example embodiments relate to a method for fabricating a semiconductor device. The method for fabricating a semiconductor device includes stacking on a substrate an etching target layer, a first mask layer, and a photoresist layer, irradiating extreme ultraviolet (EUV) radiation on the photoresist layer to form a photoresist pattern, patterning the first mask layer to form a first mask pattern using the photoresist pattern as an etching mask, and patterning the etching target layer to form a target pattern using the first mask pattern as an etching mask. The first mask layer includes at least one of a silicon layer and a titanium oxide layer.Type: GrantFiled: February 27, 2017Date of Patent: May 14, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Nam-Gun Kim, Sangmin Lee, Sinhae Do, Seok-Won Cho, Taeseop Choi, Kon Ha
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Patent number: 10224332Abstract: A semiconductor device includes a substrate with an active region, a plurality of conductive line structures on the substrate, an insulating layer separating the plurality of conductive line structures from the substrate, a contact plug between every two adjacent conductive line structures, an insulating spacer structure between each conductive line structure and a corresponding contact plug, a landing pad connected to each contact plug, and a landing pad insulation pattern having an asymmetrical shape based on a vertical axis of the landing pad that extends along a normal to the substrate. The landing pad insulation pattern includes a first portion overlapping the conductive line structures and a second portion overlapping the contact plug, the first and second portions being on opposite sides of the vertical axis.Type: GrantFiled: May 18, 2017Date of Patent: March 5, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Nam-gun Kim, Sang-min Lee, Tae-seop Choi, Kon Ha, Seung-jae Lee
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Publication number: 20180047732Abstract: A semiconductor device includes a substrate with an active region, a plurality of conductive line structures on the substrate, an insulating layer separating the plurality of conductive line structures from the substrate, a contact plug between every two adjacent conductive line structures, an insulating spacer structure between each conductive line structure and a corresponding contact plug, a landing pad connected to each contact plug, and a landing pad insulation pattern separating every two adjacent landing pads from each other, each of the landing pad insulation patterns having an asymmetrical shape based on a vertical axis of the landing pad that extends along a normal to the substrate.Type: ApplicationFiled: May 18, 2017Publication date: February 15, 2018Inventors: Nam-gun KIM, Sang-min LEE, Tae-seop CHOI, Kon HA, Seung-jae LEE
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Publication number: 20180033637Abstract: Example embodiments relate to a method for fabricating a semiconductor device. The method for fabricating a semiconductor device includes stacking on a substrate an etching target layer, a first mask layer, and a photoresist layer, irradiating extreme ultraviolet (EUV) radiation on the photoresist layer to form a photoresist pattern, patterning the first mask layer to form a first mask pattern using the photoresist pattern as an etching mask, and patterning the etching target layer to form a target pattern using the first mask pattern as an etching mask. The first mask layer includes at least one of a silicon layer and a titanium oxide layer.Type: ApplicationFiled: February 27, 2017Publication date: February 1, 2018Applicant: Samsung Electronics Co., Ltd.Inventors: Nam-Gun KIM, Sangmin LEE, Sinhae DO, Seok-Won CHO, Taeseop CHOI, Kon HA
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Publication number: 20080230389Abstract: An electrochemical detector integrated on a capillary electrophoresis chip according to the present invention includes: a first substrate having a microchannel; a second substrate adapted to mate with the first substrate and having at least one peripheral electrode for conducting electrophoresis of a sample injected along the microchannel of the first substrate, in which a separation channel is formed along the microchannel by bonding the first substrate with the second substrate; a first electrode, made of indium tin oxide (ITO), formed on the first substrate to be positioned over the separation channel; and a second electrode, made of indium tin oxide (ITO), formed on the second substrate to be positioned under the separation channel, and spaced apart from the first electrode at a predetermined interval, wherein the first electrode and the second electrode constitute a detector to measure electrical characteristics of the sample passing along the separation channel.Type: ApplicationFiled: March 24, 2008Publication date: September 25, 2008Applicant: Myongji University Industry and Academia Cooperation FoundationInventors: Kon Ha, Yong Sang Kim, Chi Jung Kang, In Je Yi