Patents by Inventor Kong Bee Tiu
Kong Bee Tiu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9305898Abstract: A semiconductor device includes a lead frame, and an integrated circuit die. The lead frame has a flag for supporting the die and leads that surround that flag and die. The lead frame also has ground ring that surrounds the flag and die. First bond wires electrically connect the die to the lead frame leads. An insulating layer is disposed on the ground ring, and a power layer is disposed on the insulating layer. The semiconductor device further includes second bond wires that connect the die to the ground ring and third bond wires that connect the die to the power layer.Type: GrantFiled: January 23, 2014Date of Patent: April 5, 2016Assignee: FREESCALE SEMICONDUCTOR, INC.Inventors: Kong Bee Tiu, Ruzaini B. Ibrahim, Wen Shi Koh
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Patent number: 9209120Abstract: A semiconductor package includes a lead frame having an interior region and leads surrounding the interior region, an integrated circuit, a region of insulating material, and a power bar. The integrated circuit, which is disposed in the interior region, has bond pads and electrical couplings (e.g., bond wires) between the bond pads and the leads. The region of insulating material is disposed on at least some of the lead frame leads and the power bar is disposed on the region of insulating material. There also are electrical couplings between the power bar and at least some of the bond pads.Type: GrantFiled: March 11, 2014Date of Patent: December 8, 2015Assignee: FREESCALE SEMICONDUCTOR, INC.Inventors: Kong Bee Tiu, Chee Seng Foong, Wai Yew Lo
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Patent number: 9190352Abstract: A semiconductor device includes a lead frame having a flag and leads that surround the flag. The leads include a dummy lead that has first and second wire bonding areas. A first die is attached on the flag and electrically connected to the first wire bonding area. The first die and the first wire bonding area are encapsulated with a molding material and a cavity with an opening is formed above the first die. The second wire bonding area is exposed in the cavity. A second die is placed in the cavity and electrically connected to the second wire bonding area such that the second die is electrically connected to the first die by way of the dummy lead.Type: GrantFiled: November 21, 2013Date of Patent: November 17, 2015Assignee: FREESCALE SEMICONDUCTOR, INC.Inventors: Kong Bee Tiu, Teck Beng Lau, Wai Yew Lo
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Publication number: 20150262924Abstract: A semiconductor package includes a lead frame having an interior region and leads surrounding the interior region, an integrated circuit, a region of insulating material, and a power bar. The integrated circuit, which is disposed in the interior region, has bond pads and electrical couplings (e.g., bond wires) between the bond pads and the leads. The region of insulating material is disposed on at least some of the lead frame leads and the power bar is disposed on the region of insulating material. There also are electrical couplings between the power bar and at least some of the bond pads.Type: ApplicationFiled: March 11, 2014Publication date: September 17, 2015Inventors: Kong Bee Tiu, Chee Seng Foong, Wai Yew Lo
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Publication number: 20150206834Abstract: A semiconductor device includes a lead frame, and an integrated circuit die. The lead frame has a flag for supporting the die and leads that surround that flag and die. The lead frame also has ground ring that surrounds the flag and die. First bond wires electrically connect the die to the lead frame leads. An insulating layer is disposed on the ground ring, and a power layer is disposed on the insulating layer. The semiconductor device further includes second bond wires that connect the die to the ground ring and third bond wires that connect the die to the power layer.Type: ApplicationFiled: January 23, 2014Publication date: July 23, 2015Inventors: KONG BEE TIU, Ruzaini B. Ibrahim, Wen Shi Koh
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Publication number: 20150137279Abstract: A semiconductor device includes a lead frame having a flag and leads that surround the flag. The leads include a dummy lead that has first and second wire bonding areas. A first die is attached on the flag and electrically connected to the first wire bonding area. The first die and the first wire bonding area are encapsulated with a molding material and a cavity with an opening is formed above the first die. The second wire bonding area is exposed in the cavity. A second die is placed in the cavity and electrically connected to the second wire bonding area such that the second die is electrically connected to the first die by way of the dummy lead.Type: ApplicationFiled: November 21, 2013Publication date: May 21, 2015Inventors: Kong Bee Tiu, Teck Beng Lau, Wai Yew Lo
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Patent number: 8981541Abstract: A Quad Flat Package (QFP) semiconductor device has a multi-stepped lead frame for forming rows of external contacts. A semiconductor die is attached to a die pad of the lead frame and electrically connected to lead with bond wires. The die and bond wires are encapsulated with a mold compound and then multiple cuts are made to the lead frame to form the rows of external contacts.Type: GrantFiled: July 10, 2013Date of Patent: March 17, 2015Assignee: Freescale Semiconductor, Inc.Inventors: Kong Bee Tiu, Ruzaini B. Ibrahim, Wai Yew Lo
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Publication number: 20150014833Abstract: A Quad Flat Package (QFP) semiconductor device has a multi-stepped lead frame for forming rows of external contacts. A semiconductor die is attached to a die pad of the lead frame and electrically connected to lead with bond wires. The die and bond wires are encapsulated with a mold compound and then multiple cuts are made to the lead frame to form the rows of external contacts.Type: ApplicationFiled: July 10, 2013Publication date: January 15, 2015Inventors: Kong Bee Tiu, Ruzaini B. Ibrahim, Wai Yew Lo
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Publication number: 20140374848Abstract: A semiconductor sensor device is packaged using a lid in which one or more dies are mounted to a substrate within the lid housing and one or more other dies are mounted to the substrate outside of the lid housing. The dies located outside of the lid housing may be encapsulated in a molding compound. In one embodiment, the lid has a vent hole and an active region of a pressure-sensing die located inside the lid housing is covered by a pressure-sensitive gel that together enable ambient atmospheric pressure immediately outside the sensor device to reach the active region of the pressure-sensing die. The sensor device may also have one or more other types of sensor dies, such as an acceleration-sensing die, to form a multi-sensor device.Type: ApplicationFiled: June 24, 2013Publication date: December 25, 2014Inventors: Wen Shi Koh, Wai Yew Lo, Kong Bee Tiu
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Patent number: 7261230Abstract: An improved method of bonding an insulated wire (14) that has one end connected to a first bond pad (16) to a second bond pad (18) includes moving a tip of a capillary (20) holding the bond wire (14) over the surface of the second bond pad (18) such that the bond wire (14) is rubbed between the capillary tip (20) and the second bond pad (18), which tears the bond wire insulation so that at least a portion of a metal core of the wire (14) contacts the second bond pad (18). The wire (14) is then bonded to the second pad (18) using thermocompression bonding. The tip of the capillary (20) is roughened to enhance the tearing of the bond wire insulation.Type: GrantFiled: August 29, 2003Date of Patent: August 28, 2007Assignee: Freescale Semiconductor, Inc.Inventors: Fuaida Harun, Chiaw Mong Chan, Lan Chu Tan, Lau Teck Beng, Kong Bee Tiu, Soo San Yong
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Patent number: 7211466Abstract: A stacked multichip package (100) has a base carrier (102) having a top side (108) and a bottom side (110), a bottom integrated circuit die (104) having a bottom surface (112) attached to the base carrier top side (108), and an opposing, top surface (114). The top surface (114) has a peripheral area including a plurality of first bonding pads and a central area (120). A bead (124) is formed on the top surface (114) of the bottom die (104) between the peripheral area and the central area (120). A top integrated circuit die (106) having a bottom surface is positioned over the bottom die (104) and the bottom surface of the top die (106) is attached to the top surface (114) of the bottom die (104) via the bead (124). The bead (124) maintains a predetermined spacing between the bottom die (104) and the top die (106) so that wirebonds of first wires (122) connecting the bottom die (104) to the base carrier (102) are not damaged when the top die (106) is attached to the bottom die (104).Type: GrantFiled: January 31, 2005Date of Patent: May 1, 2007Assignee: Freescale Semiconductor, Inc.Inventors: Wai Yew Lo, Azhar Bin Aripin, Kong Bee Tiu
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Publication number: 20070026573Abstract: A method of making a stacked die package (50) includes attaching and electrically connecting a first integrated circuit (IC) die (52) to a base carrier (56). A plurality of successive layers (54A, 54B and 54C) of an adhesive material (54) is formed on the first die (52). A second die (72) is attached to the first die (52) with the adhesive material (54) such that the successive layers of adhesive material (54A, 54B and 54C) maintain a predetermined spacing (H) between the first die (52) and the second die (72). The second die (72) is electrically connected to the base carrier (56).Type: ApplicationFiled: July 28, 2005Publication date: February 1, 2007Inventors: Aminuddin Ismail, Wai Yew Lo, Kong Bee Tiu, Cheng Choi Yong
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Patent number: 7160755Abstract: A method of forming a substrateless semiconductor package (10) includes forming a carrier (16) on a base plate (12) and attaching an integrated circuit (IC) die (32) to the carrier (16). The IC die (32) then is electrically connected to the carrier (16). A molding operation is performed to encapsulate the IC die (32), the electrical connections (36) and the carrier (16). Thereafter, the base plate (12) is removed.Type: GrantFiled: April 18, 2005Date of Patent: January 9, 2007Assignee: Freescale Semiconductor, Inc.Inventors: Wai Yew Lo, Cheng Choi Yong, Kong Bee Tiu
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Patent number: 6885093Abstract: A stacked multichip package (100) has a base carrier (102) having a top side (108) and a bottom side (110), a bottom integrated circuit die (104) having a bottom surface (112) attached to the base carrier top side (108), and an opposing, top surface (114). The top surface (114) has a peripheral area including a plurality of first bonding pads and a central area (120). A bead (124) is formed on the top surface (114) of the bottom die (104) between the peripheral area and the central area (120). A top integrated circuit die (106) having a bottom surface is positioned over the bottom die (104) and the bottom surface of the top die (106) is attached to the top surface (114) of the bottom die (104) via the bead (124). The bead (124) maintains a predetermined spacing between the bottom die (104) and the top die (106) so that wirebonds of first wires (122) connecting the bottom die (104) to the base carrier (102) are not damaged when the top die (106) is attached to the bottom die (104).Type: GrantFiled: February 28, 2002Date of Patent: April 26, 2005Assignee: Freescale Semiconductor, Inc.Inventors: Wai Yew Lo, Azhar Bin Aripin, Kong Bee Tiu
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Patent number: 6854637Abstract: An electrical connection for connecting a bond pad of a first device and a bond pad of a second device with an insulated or coated wire. The electrical connection includes a first wirebond securing a first portion of the insulated bond wire to the first device bond pad. A second wirebond secures a second portion of the insulated bond wire to the second device bond pad. A bump is formed over the second wirebond, and the bump is offset from the second wirebond. The offset bump enhances the second bond, providing it with increased wire peel strength.Type: GrantFiled: February 20, 2003Date of Patent: February 15, 2005Assignee: Freescale Semiconductor, Inc.Inventors: Fuaida Harun, Kong Bee Tiu
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Publication number: 20040164126Abstract: An electrical connection for connecting a bond pad of a first device and a bond pad of a second device with an insulated or coated wire. The electrical connection includes a first wirebond securing a first portion of the insulated bond wire to the first device bond pad. A second wirebond secures a second portion of the insulated bond wire to the second device bond pad. A bump is formed over the second wirebond, and the bump is offset from the second wirebond. The offset bump enhances the second bond, providing it with increased wire peel strength.Type: ApplicationFiled: February 20, 2003Publication date: August 26, 2004Inventors: Fuaida Harun, Kong Bee Tiu
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Publication number: 20030230796Abstract: An electrical connection for connecting multiple bonding pads of different devices. The electrical connection includes a first bonding pad on a first device and a bump disposed on the first bonding pad. A first wire is stitch bonded to the bump on the first device and electrically connected to a bonding pad of a second device. A second wire is ball bonded to the stitch bond of the first wire. The second wire is also electrically connected to a bonding pad of a third device. Thus, the second and third devices are connected to a single bonding pad of the first device. The size of the bonding pad is not unnecessarily increased to accommodate multiple wire bonds. Further, additional wires may be stitch bonded between the first stitch bond and the ball bond.Type: ApplicationFiled: June 12, 2002Publication date: December 18, 2003Inventors: Aminuddin Ismail, Lan Chu Tan, Kong Bee Tiu, Cheng Choi Yong
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Publication number: 20030160312Abstract: A stacked multichip package (100) has a base carrier (102) having a top side (108) and a bottom side (110), a bottom integrated circuit die (104) having a bottom surface (112) attached to the base carrier top side (108), and an opposing, top surface (114). The top surface (114) has a peripheral area including a plurality of first bonding pads and a central area (120). A bead (124) is formed on the top surface (114) of the bottom die (104) between the peripheral area and the central area (120). A top integrated circuit die (106) having a bottom surface is positioned over the bottom die (104) and the bottom surface of the top die (106) is attached to the top surface (114) of the bottom die (104) via the bead (124). The bead (124) maintains a predetermined spacing between the bottom die (104) and the top die (106) so that wirebonds of first wires (122) connecting the bottom die (104) to the base carrier (102) are not damaged when the top die (106) is attached to the bottom die (104).Type: ApplicationFiled: February 28, 2002Publication date: August 28, 2003Inventors: Wai Yew Lo, Azhar Bin Aripin, Kong Bee Tiu