Abstract: A system for verifying that device fingers of a semiconductor circuit have been properly represented by a corresponding layout diagram. The system determines a plurality of sub-circuits, from within a netlist of a schematic diagram, to be verified. Each sub-circuit of the plurality of sub-circuits includes a multi-finger device. The system also determines a first number of fingers included in the plurality of sub-circuits as represented by the schematic diagram. The system also determines a second number of fingers included in the plurality of sub-circuits as represented by the corresponding layout diagram. The system compares the first number of fingers against the second number of fingers. The system reports an error if the first number of fingers does not correspond to the second number of fingers.

Abstract: The present invention describes a method and apparatus for placing flops in a complex circuit design. Initially, the method calculates a physical range for every net that requires a flop, within which the flop can be placed satisfying the timing requirement. After the physical range is defined, the method groups these flops and determines a block where these grouped flops can be placed. Grouping these flops into one block (flop station) can preserve a compact layout for the design. The flops are then connected to appropriate nets.

Abstract: The present invention describes a method and apparatus for placing flops in a complex circuit design. Initially, the method calculates a physical range for every net that requires a flop, within which the flop can be placed satisfying the timing requirement. After the physical range is defined, the method groups these flops and determines a block where these grouped flops can be placed. Grouping these flops into one block (flop station) can preserve a compact layout for the design. The flops are then connected to appropriate nets.

Abstract: Provided is a method, a system and a computer product to translate electronic schematic files between computer-aided software design tools. One embodiment of the invention includes converting source files, containing electronic schematic information, into output files. Creating, from the source files, export files that omit a sub-portion of the schematic information, defining omitted data, each of the export files having a file name associated therewith. Appending, to the file name of the export files, data concerning the omitted information to form an appended file name. The export files are converted to the output files retained in the appended file name. The appended name is diminished so as to remove all information therefrom, excepting information corresponding to the omitted information.

Abstract: Provided is a method, a system and a computer product to translate electronic schematic files between computer-aided software design tools. One embodiment of the invention includes converting source files, containing electronic schematic information, into output files. Creating, from the source files, export files that omit a sub-portion of the schematic information, defining omitted data, each of the export files having a file name associated therewith. Appending, to the file name of the export files, data concerning the omitted information to form an appended file name. The export files are converted to the output files retained in the appended file name. The appended name is diminished so as to remove all information therefrom, excepting information corresponding to the omitted information.

Abstract: Method and system for providing a netlist driven integrated router in a non-netlist driven environment for microprocessor designs includes retrieving top level netlist for the existing microprocessor design from the top level database and the design parameters for the new microprocessor design, and translating these netlist and design parameters at the front end so that the resulting data can be provided to an integrated router which is configured to generate re-routes for the new microprocessor design based on the top level netlist and the design parameters, where the generated re-routes are provided to a back end for translating the re-routes to new top level netlist and merging the new top level netlist with the existing top level netlist database.

Abstract: The present invention organizes the circuits on a VLSI chip into clusters. A number of channels exist in-between the clusters. Blocks of repeaters are used in a linear array, and are placed adjacent the edges of the clusters where repeaters are estimated to be needed. The repeater cells themselves are preferably formed to have a width less than or equal to the width of a line track for routing lines such that an array of repeater cells can be lined up with an array of routing lines in a bus.