Patents by Inventor Kong-Pin Chang
Kong-Pin Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11869800Abstract: A method for fabricating a semiconductor device includes receiving a silicon substrate having an isolation feature disposed on the substrate and a well adjacent the isolation feature, wherein the well includes a first dopant. The method also includes etching a recess to remove a portion of the well and epitaxially growing a silicon layer (EPI layer) in the recess to form a channel, wherein the channel includes a second dopant. The method also includes forming a barrier layer between the well and the EPI layer, the barrier layer including at least one of either silicon carbon or silicon oxide. The barrier layer can be formed either before or after the channel. The method further includes forming a gate electrode disposed over the channel and forming a source and drain in the well.Type: GrantFiled: June 22, 2020Date of Patent: January 9, 2024Inventors: Harry-Hak-Lay Chuang, Bao-Ru Young, Wei Cheng Wu, Meng-Fang Hsu, Kong-Pin Chang, Chia Ming Liang
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Publication number: 20230377942Abstract: A method for fabricating a semiconductor device includes receiving a silicon substrate having an isolation feature disposed on the substrate and a well adjacent the isolation feature, wherein the well includes a first dopant. The method also includes etching a recess to remove a portion of the well and epitaxially growing a silicon layer (EPI layer) in the recess to form a channel, wherein the channel includes a second dopant. The method also includes forming a barrier layer between the well and the EPI layer, the barrier layer including at least one of either silicon carbon or silicon oxide. The barrier layer can be formed either before or after the channel. The method further includes forming a gate electrode disposed over the channel and forming a source and drain in the well.Type: ApplicationFiled: July 27, 2023Publication date: November 23, 2023Inventors: Harry-Hak-Lay Chuang, Bao-Ru Young, Wei Cheng Wu, Meng-Fang Hsu, Kong-Pin Chang, Chia Ming Liang
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Publication number: 20200321238Abstract: A method for fabricating a semiconductor device includes receiving a silicon substrate having an isolation feature disposed on the substrate and a well adjacent the isolation feature, wherein the well includes a first dopant. The method also includes etching a recess to remove a portion of the well and epitaxially growing a silicon layer (EPI layer) in the recess to form a channel, wherein the channel includes a second dopant. The method also includes forming a barrier layer between the well and the EPI layer, the barrier layer including at least one of either silicon carbon or silicon oxide. The barrier layer can be formed either before or after the channel. The method further includes forming a gate electrode disposed over the channel and forming a source and drain in the well.Type: ApplicationFiled: June 22, 2020Publication date: October 8, 2020Inventors: Harry-Hak-Lay Chuang, Bao-Ru Young, Wei Cheng Wu, Meng-Fang Hsu, Kong-Pin Chang, Chia Ming Liang
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Patent number: 10692750Abstract: A method for fabricating a semiconductor device includes receiving a silicon substrate having an isolation feature disposed on the substrate and a well adjacent the isolation feature, wherein the well includes a first dopant. The method also includes etching a recess to remove a portion of the well and epitaxially growing a silicon layer (EPI layer) in the recess to form a channel, wherein the channel includes a second dopant. The method also includes forming a barrier layer between the well and the EPI layer, the barrier layer including at least one of either silicon carbon or silicon oxide. The barrier layer can be formed either before or after the channel. The method further includes forming a gate electrode disposed over the channel and forming a source and drain in the well.Type: GrantFiled: May 14, 2018Date of Patent: June 23, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Harry-Hak-Lay Chuang, Bao-Ru Young, Wei Cheng Wu, Meng-Fang Hsu, Kong-Pin Chang, Chia Ming Liang
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Publication number: 20180269099Abstract: A method for fabricating a semiconductor device includes receiving a silicon substrate having an isolation feature disposed on the substrate and a well adjacent the isolation feature, wherein the well includes a first dopant. The method also includes etching a recess to remove a portion of the well and epitaxially growing a silicon layer (EPI layer) in the recess to form a channel, wherein the channel includes a second dopant. The method also includes forming a barrier layer between the well and the EPI layer, the barrier layer including at least one of either silicon carbon or silicon oxide. The barrier layer can be formed either before or after the channel. The method further includes forming a gate electrode disposed over the channel and forming a source and drain in the well.Type: ApplicationFiled: May 14, 2018Publication date: September 20, 2018Inventors: Harry-Hak-Lay Chuang, Bao-Ru Young, Wei Cheng Wu, Meng-Fang Hsu, Kong-Pin Chang, Chia Ming Liang
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Patent number: 9972524Abstract: A method for fabricating a semiconductor device includes receiving a silicon substrate having an isolation feature disposed on the substrate and a well adjacent the isolation feature, wherein the well includes a first dopant. The method also includes etching a recess to remove a portion of the well and epitaxially growing a silicon layer (EPI layer) in the recess to form a channel, wherein the channel includes a second dopant. The method also includes forming a barrier layer between the well and the EPI layer, the barrier layer including at least one of either silicon carbon or silicon oxide. The barrier layer can be formed either before or after the channel. The method further includes forming a gate electrode disposed over the channel and forming a source and drain in the well.Type: GrantFiled: March 11, 2013Date of Patent: May 15, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Harry-Hak-Lay Chuang, Bao-Ru Young, Wei Cheng Wu, Meng-Fang Hsu, Kong-Pin Chang, Chia Ming Liang
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Patent number: 9911805Abstract: Some embodiments of the present disclosure relate to a method. In this method, a semiconductor substrate, which has an active region disposed in the semiconductor substrate, is received. A shallow trench isolation (STI) structure is formed to laterally surround the active region. An upper surface of the active region bounded by the STI structure is recessed to below an upper surface of the STI structure. The recessed upper surface extends continuously between inner sidewalls of the STI structure and leaves upper portions of the inner sidewalls of the STI structure exposed. A semiconductor layer is epitaxially grown on the recessed surface of the active region between the inner sidewalls of the STI structure. A gate dielectric is formed over the epitaxially-grown semiconductor layer. A conductive gate electrode is formed over the gate dielectric.Type: GrantFiled: November 11, 2016Date of Patent: March 6, 2018Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Harry-Hak-Lay Chuang, Bao-Ru Young, Wei Cheng Wu, Kong-Pin Chang, Chia Ming Liang, Meng-Fang Hsu, Ching-Feng Fu, Shih-Ting Hung
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Publication number: 20170062559Abstract: Some embodiments of the present disclosure relate to a method. In this method, a semiconductor substrate, which has an active region disposed in the semiconductor substrate, is received. A shallow trench isolation (STI) structure is formed to laterally surround the active region. An upper surface of the active region bounded by the STI structure is recessed to below an upper surface of the STI structure. The recessed upper surface extends continuously between inner sidewalls of the STI structure and leaves upper portions of the inner sidewalls of the STI structure exposed. A semiconductor layer is epitaxially grown on the recessed surface of the active region between the inner sidewalls of the STI structure. A gate dielectric is formed over the epitaxially-grown semiconductor layer. A conductive gate electrode is formed over the gate dielectric.Type: ApplicationFiled: November 11, 2016Publication date: March 2, 2017Inventors: Harry-Hak-Lay Chuang, Bao-Ru Young, Wei Cheng Wu, Kong-Pin Chang, Chia Ming Liang, Meng-Fang Hsu, Ching-Feng Fu, Shih-Ting Hung
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Patent number: 9502533Abstract: Some embodiments of the present disclosure relate to a method. In this method, a semiconductor substrate, which has an active region disposed in the semiconductor substrate, is received. A shallow trench isolation (STI) structure is formed to laterally surround the active region. An upper surface of the active region bounded by the STI structure is recessed to below an upper surface of the STI structure. The recessed upper surface extends continuously between inner sidewalls of the STI structure and leaves upper portions of the inner sidewalls of the STI structure exposed. A semiconductor layer is epitaxially grown on the recessed surface of the active region between the inner sidewalls of the STI structure. A gate dielectric is formed over the epitaxially-grown semiconductor layer. A conductive gate electrode is formed over the gate dielectric.Type: GrantFiled: August 26, 2015Date of Patent: November 22, 2016Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Harry-Hak-Lay Chuang, Bao-Ru Young, Wei Cheng Wu, Kong-Pin Chang, Chia Ming Liang, Meng-Fang Hsu, Ching-Feng Fu, Shih-Ting Hung
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Publication number: 20150364575Abstract: Some embodiments of the present disclosure relate to a method. In this method, a semiconductor substrate, which has an active region disposed in the semiconductor substrate, is received. A shallow trench isolation (STI) structure is formed to laterally surround the active region. An upper surface of the active region bounded by the STI structure is recessed to below an upper surface of the STI structure. The recessed upper surface extends continuously between inner sidewalls of the STI structure and leaves upper portions of the inner sidewalls of the STI structure exposed. A semiconductor layer is epitaxially grown on the recessed surface of the active region between the inner sidewalls of the STI structure. A gate dielectric is formed over the epitaxially-grown semiconductor layer. A conductive gate electrode is formed over the gate dielectric.Type: ApplicationFiled: August 26, 2015Publication date: December 17, 2015Inventors: Harry-Hak-Lay Chuang, Bao-Ru Young, Wei Cheng Wu, Kong-Pin Chang, Chia Ming Liang, Meng-Fang Hsu, Ching-Feng Fu, Shih-Ting Hung
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Patent number: 9129823Abstract: The embodiments described provide methods and semiconductor device areas for etching an active area region on a semiconductor body and epitaxially depositing a semiconductor layer overlying the active region. The methods enable the mitigation or elimination of problems encountered in subsequent manufacturing associated with STI divots.Type: GrantFiled: April 1, 2013Date of Patent: September 8, 2015Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Harry-Hak-Lay Chuang, Bao-Ru Young, Wei Cheng Wu, Kong-Pin Chang, Chia Ming Liang, Meng-Fang Hsu, Ching-Feng Fu, Shih-Ting Hung
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Publication number: 20140264725Abstract: The embodiments described provide methods and semiconductor device areas for etching an active area region on a semiconductor body and epitaxially depositing a semiconductor layer overlying the active region. The methods enable the mitigation or elimination of problems encountered in subsequent manufacturing associated with STI divots.Type: ApplicationFiled: April 1, 2013Publication date: September 18, 2014Inventors: Harry-Hak-Lay Chuang, Bao-Ru Young, Wei Cheng Wu, Kong-Pin Chang, Chia Ming Liang, Meng-Fang Hsu, Ching-Feng Fu, Shih-Ting Hung