Patents by Inventor Kong-Soo Lee
Kong-Soo Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12342588Abstract: A semiconductor device includes a channel layer disposed on a substrate and a gate structure formed on or under the channel layer. The channel layer includes a single-layer oxide semiconductor material, the channel layer includes indium (In), gallium (Ga), and oxygen (O), the channel layer includes a first region, a second region, and a third region, the third region contacting the gate structure, a second region between the first region and the third region, the first region is the closer to the substrate than the second region and the third region, each of the first region and the third region has a concentration of Ga higher than a concentration of In, and the second region has a concentration of In higher than a concentration of Ga.Type: GrantFiled: June 24, 2022Date of Patent: June 24, 2025Assignee: Samsung Electronics Co., Ltd.Inventors: Teawon Kim, Yurim Kim, Seohee Park, Kong-Soo Lee, Yong Suk Tak
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Patent number: 12213304Abstract: A semiconductor device includes: a substrate; a conductive line extending on the substrate in a first horizontal direction; an isolation insulating layer extending on the substrate and the conductive line in a second horizontal direction intersecting with the first horizontal direction, and defining a channel trench extending through the isolation insulating layer from an upper surface of the isolation insulating layer to a lower surface of the isolation insulating layer; a crystalline oxide semiconductor layer extending along at least a portion of an inner side surface of the channel trench and at least a portion of a bottom surface of the channel trench and coming in contact with the conductive line; and a gate electrode extending on the crystalline oxide semiconductor layer inside the channel trench in the second horizontal direction.Type: GrantFiled: May 26, 2022Date of Patent: January 28, 2025Assignee: Samsung Electronics Co., Ltd.Inventors: Teawon Kim, Yurim Kim, Seohee Park, Kong-Soo Lee, Yong Suk Tak
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Patent number: 11805641Abstract: A method for manufacturing a semiconductor device is provided.Type: GrantFiled: January 4, 2022Date of Patent: October 31, 2023Inventors: Sa Hwan Hong, Jong Myeong Kim, Myeong Jin Bang, Kong Soo Lee, Han Mei Choi, Ho Kyun An
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Publication number: 20230137072Abstract: A semiconductor device includes a channel layer disposed on a substrate and a gate structure formed on or under the channel layer. The channel layer includes a single-layer oxide semiconductor material, the channel layer includes indium (In), gallium (Ga), and oxygen (O), the channel layer includes a first region, a second region, and a third region, the third region contacting the gate structure, a second region between the first region and the third region, the first region is the closer to the substrate than the second region and the third region, each of the first region and the third region has a concentration of Ga higher than a concentration of In, and the second region has a concentration of In higher than a concentration of Ga.Type: ApplicationFiled: June 24, 2022Publication date: May 4, 2023Applicant: Samsung Electronics Co., Ltd.Inventors: Teawon KIM, Yurim KIM, Seohee PARK, Kong-Soo LEE, Yong Suk TAK
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Publication number: 20230134099Abstract: A semiconductor device includes: a substrate; a conductive line extending on the substrate in a first horizontal direction; an isolation insulating layer extending on the substrate and the conductive line in a second horizontal direction intersecting with the first horizontal direction, and defining a channel trench extending through the isolation insulating layer from an upper surface of the isolation insulating layer to a lower surface of the isolation insulating layer; a crystalline oxide semiconductor layer extending along at least a portion of an inner side surface of the channel trench and at least a portion of a bottom surface of the channel trench and coming in contact with the conductive line; and a gate electrode extending on the crystalline oxide semiconductor layer inside the channel trench in the second horizontal direction.Type: ApplicationFiled: May 26, 2022Publication date: May 4, 2023Applicant: Samsung Electronics Co., Ltd.Inventors: Teawon KIM, Yurim KIM, Seohee PARK, Kong-Soo LEE, Yong Suk TAK
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Publication number: 20230116342Abstract: A semiconductor device is provided. A semiconductor device includes: a first active pattern spaced apart from a substrate and extending in a first direction; a second active pattern spaced apart further from the substrate than the first active pattern and extending in the first direction; a gate structure on the substrate, the gate structure extending in a second direction crossing the first direction and penetrating the first active pattern and the second active pattern; a first source/drain region on at least one side surface of the gate structure and connected to the first active pattern; a second source/drain region on at least one side surface of the gate structure and connected to the second active pattern; and a buffer layer between the substrate and the first active pattern, the buffer layer containing germanium.Type: ApplicationFiled: June 1, 2022Publication date: April 13, 2023Inventors: Won Hee Choi, Sung Uk Jang, Dong Suk Shin, Bong Jin Kuh, Kong Soo Lee
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Publication number: 20230035916Abstract: A semiconductor device includes a conductive line that extends in a first direction on a substrate, a first oxide semiconductor layer, including a first crystalline oxide semiconductor material containing a first metal element, on the conductive line, a second oxide semiconductor layer, which is in physical contact with the first oxide semiconductor layer and is connected to the conductive line, on the conductive line, a gate electrode that extends in a second direction, which crosses the first direction, on a side of the second oxide semiconductor layer, and a capacitor structure connected to the second oxide semiconductor layer on the second oxide semiconductor layer and the gate electrode, wherein the second oxide semiconductor layer includes a second crystalline oxide semiconductor material containing the first metal element and second and third metal elements, which are different from the first metal element.Type: ApplicationFiled: March 3, 2022Publication date: February 2, 2023Inventors: Tea Won Kim, Hyung Joon Kim, Yong-Suk Tak, Yu Rim Kim, Kong Soo Lee
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Publication number: 20220336483Abstract: A method for manufacturing a semiconductor device is provided.Type: ApplicationFiled: January 4, 2022Publication date: October 20, 2022Inventors: Sa Hwan HONG, Jong Myeong KIM, Myeong Jin BANG, Kong Soo LEE, Han Mei CHOI, Ho Kyun AN
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Patent number: 10892263Abstract: Methods of fabricating a semiconductor device are provided. The methods may include forming a gate structure on a core-peri region of a substrate. The substrate may further include a cell region. The methods may also include forming a gate spacer on a sidewall of the gate structure, forming a first impurity region adjacent the gate spacer in the core-peri region of the substrate by performing a first ion implantation process, removing the gate spacer, forming a second impurity region in the core-peri region of the substrate between the gate structure and the first impurity region by performing a second ion implantation process, forming a stress film on the gate structure, an upper surface of the first impurity region, and an upper surface of the second impurity region, and forming a recrystallization region by crystallizing the first impurity region and the second impurity region by performing an annealing process.Type: GrantFiled: February 8, 2019Date of Patent: January 12, 2021Inventors: Hoi Sung Chung, Tae Sung Kang, Dong Suk Shin, Kong Soo Lee, Jun-Won Lee
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Patent number: 10553449Abstract: A method of forming a pattern includes forming an etch target layer on a substrate, forming sacrificial patterns on the etch target layer, the sacrificial patterns including a carbon-containing material, providing a silicon-sulfur compound or a sulfur-containing gas onto the sacrificial patterns to form a seed layer, providing a silicon precursor onto the seed layer to form silicon-containing mask patterns, and at least partially etching the etch target layer using the mask patterns.Type: GrantFiled: September 11, 2017Date of Patent: February 4, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Sun-Hye Hwang, Youn-Joung Cho, Won-Woong Chung, Nam-Gun Kim, Kong-Soo Lee, Badro Im, Yoon-Chul Cho
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Publication number: 20190386008Abstract: Methods of fabricating a semiconductor device are provided. The methods may include forming a gate structure on a core-peri region of a substrate. The substrate may further include a cell region. The methods may also include forming a gate spacer on a sidewall of the gate structure, forming a first impurity region adjacent the gate spacer in the core-peri region of the substrate by performing a first ion implantation process, removing the gate spacer, forming a second impurity region in the core-peri region of the substrate between the gate structure and the first impurity region by performing a second ion implantation process, forming a stress film on the gate structure, an upper surface of the first impurity region, and an upper surface of the second impurity region, and forming a recrystallization region by crystallizing the first impurity region and the second impurity region by performing an annealing process.Type: ApplicationFiled: February 8, 2019Publication date: December 19, 2019Inventors: Hoi Sung Chung, Tae Sung Kang, Dong Suk Shin, Kong Soo Lee, Jun-Won Lee
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Publication number: 20180102260Abstract: A method of forming a pattern includes forming an etch target layer on a substrate, forming sacrificial patterns on the etch target layer, the sacrificial patterns including a carbon-containing material, providing a silicon-sulfur compound or a sulfur-containing gas onto the sacrificial patterns to form a seed layer, providing a silicon precursor onto the seed layer to form silicon-containing mask patterns, and at least partially etching the etch target layer using the mask patterns.Type: ApplicationFiled: September 11, 2017Publication date: April 12, 2018Inventors: Sun-Hye HWANG, Youn-Joung CHO, Won-Woong CHUNG, Nam-Gun KIM, Kong-Soo LEE, Badro IM, Yoon-Chul CHO
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Patent number: 9646971Abstract: Semiconductor devices and fabricating methods thereof are provided. A semiconductor device may include a substrate, a metal layer on the substrate, a seed layer on the metal layer, a nanowire including a pillar shape on the seed layer, a dielectric film conformally covering the nanowire, and an electrode film on the dielectric film.Type: GrantFiled: May 24, 2016Date of Patent: May 9, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Dong-Hyun Im, Han-Jin Lim, Jin-Won Ma, Kong-Soo Lee, Ki-Vin Im
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Publication number: 20170062435Abstract: Semiconductor devices and fabricating methods thereof are provided. A semiconductor device may include a substrate, a metal layer on the substrate, a seed layer on the metal layer, a nanowire including a pillar shape on the seed layer, a dielectric film conformally covering the nanowire, and an electrode film on the dielectric film.Type: ApplicationFiled: May 24, 2016Publication date: March 2, 2017Inventors: Dong-Hyun IM, Han-Jin LIM, Jin-Won MA, Kong-Soo LEE, Ki-Vin IM
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Patent number: 9449973Abstract: A semiconductor device includes a substrate; a first inverter disposed on the substrate and receiving a voltage from any one of a bit line and a complementary bit line; a semiconductor layer disposed on the first inverter; and first and third switch devices disposed on the semiconductor layer and adjusting a threshold voltage of the first inverter to a voltage level of any one of the bit line and the complementary bit line.Type: GrantFiled: April 28, 2014Date of Patent: September 20, 2016Assignee: Samsung Electronics Co., Ltd.Inventors: Han-jin Lim, Kong-soo Lee, Seok-woo Nam, Dong-chan Kim, Soo-jin Hong
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Patent number: 9202844Abstract: A semiconductor device includes a lower interconnection having second conductivity-type impurities on a substrate having first conductivity-type impurities. A switching device is on the lower interconnection. A first blocking layer is provided between the lower interconnection and the switching device. The first blocking layer includes carbon (C), germanium (Ge), or a combination thereof. A second blocking layer may be provided between the substrate and the lower interconnection.Type: GrantFiled: August 14, 2013Date of Patent: December 1, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Jae-Jong Han, Yoon-Goo Kang, Won-Seok Yoo, Kong-Soo Lee, Han-Jin Lim, Seong-Hoon Jeong
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Patent number: 8987694Abstract: Semiconductor devices, and methods of manufacturing the same, include a field region in a semiconductor substrate to define an active region. An interlayer insulating layer is on the semiconductor substrate. A semiconductor pattern is within a hole vertically extending through the interlayer insulating layer. The semiconductor pattern is in contact with the active region. A barrier region is between the semiconductor pattern and the interlayer insulating layer. The barrier region includes a first buffer dielectric material and a barrier dielectric material. The first buffer dielectric material is between the barrier dielectric material and the semiconductor pattern, and the barrier dielectric material is spaced apart from both the semiconductor pattern and the active region.Type: GrantFiled: December 28, 2012Date of Patent: March 24, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Jae-Jong Han, Kong-Soo Lee, Yoon-Goo Kang, Ho-Kyun An, Seong-Hoon Jeong
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Publication number: 20150060862Abstract: A semiconductor device includes a substrate; a first inverter disposed on the substrate and receiving a voltage from any one of a bit line and a complementary bit line; a semiconductor layer disposed on the first inverter; and first and third switch devices disposed on the semiconductor layer and adjusting a threshold voltage of the first inverter to a voltage level of any one of the bit line and the complementary bit line.Type: ApplicationFiled: April 28, 2014Publication date: March 5, 2015Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Han-jin LIM, Kong-soo LEE, Seok-woo NAM, Dong-chan KIM, Soo-jin HONG
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Publication number: 20140158964Abstract: A semiconductor device includes a lower interconnection having second conductivity-type impurities on a substrate having first conductivity-type impurities. A switching device is on the lower interconnection. A first blocking layer is provided between the lower interconnection and the switching device. The first blocking layer includes carbon (C), germanium (Ge), or a combination thereof. A second blocking layer may be provided between the substrate and the lower interconnection.Type: ApplicationFiled: August 14, 2013Publication date: June 12, 2014Inventors: Jae-Jong HAN, Yoon-Goo Kang, Won-Seok Yoo, Kong-Soo Lee, Han-Jin Lim, Seong-Hoon Jeong
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Patent number: 8329539Abstract: In a semiconductor device having a recessed gate electrode and a method of fabricating the same, a channel trench is formed in a semiconductor substrate by etching the semiconductor substrate. A first semiconductor layer is formed on the semiconductor substrate that fills the channel trench. A second semiconductor layer is formed on the first semiconductor layer, the second semiconductor layer having a lower impurity concentration than the first semiconductor layer.Type: GrantFiled: May 8, 2006Date of Patent: December 11, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Dae-Won Ha, Kong-Soo Lee, Sung-Sam Lee, Sang-Hyun Lee, Min-Young Shim