Patents by Inventor Kong Yang

Kong Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250078879
    Abstract: Disclosed is an interface circuit and a semiconductor device including the same. The interface circuit may include a data pad, a first driving circuit connected between the data pad and a first supply node, and configured to adjust a first resistance value applied between the data pad and the first supply node according to termination modes and selectively drive the data pad with a first supply voltage, and a first tuning circuit connected between the first supply node and a first voltage supply terminal, and configured to tune the first resistance value according to the termination modes.
    Type: Application
    Filed: January 10, 2024
    Publication date: March 6, 2025
    Inventors: In Seok KONG, Gwan Woo KIM, Keun Seon AHN, Eun Ho YANG, Sung Hwa OK, Eun Ji CHOI, Jun Ho HONG
  • Patent number: 12237837
    Abstract: A signal generation apparatus includes a glitch rejection circuit including n m-stage inverters coupled in series, and configured to receive an input signal and perform an inverting operation on the input signal, based on a plurality of voltage signals, to generate an output signal and adjust switching threshold voltages of the m-stage inverters, based on the plurality of voltage signals, to generate the glitch-removed output signal, when a glitch occurs in the input signal, a level detection circuit to detect a logic level of the output signal provided from the glitch rejection circuit to generate a level detection signal and a complementary level detection signal, and a voltage signal generation circuit configured to receive the input signal, a complementary input signal, the level detection signal, and the complementary level detection signal to generate the plurality of voltage signals and provide the plurality of voltage signals to the glitch rejection circuit.
    Type: Grant
    Filed: December 20, 2022
    Date of Patent: February 25, 2025
    Assignee: SK hynix Inc.
    Inventors: Jaehyeong Hong, Junseo Jang, In Seok Kong, Soon Sung An, Dae Ho Yang, Kwan Su Shon, Yo Han Jeong
  • Patent number: 12225139
    Abstract: A method and device for issuing an identity certificate to a blockchain node in a blockchain network includes issuing a first identity certificate to a first terminal. a second identity certificate issuance request that is from the first terminal and that is made by using the first identity certificate is received and a second identity certificate is issued to the first terminal, which forwards the second identity certificate to a second terminal. A third identity certificate issuance request that is from the second terminal and that is made by using the second identity certificate is received and a third identity certificate is issued to the second terminal, which forwards the third identity certificate to a third terminal.
    Type: Grant
    Filed: February 15, 2024
    Date of Patent: February 11, 2025
    Assignee: TENCENT TECHNOLOGY (SHENZHEN) COMPANY LIMITED
    Inventors: Mao Cai Li, Zong You Wang, Kai Ban Zhou, Chang Qing Yang, Hu Lan, Li Kong, Jin Song Zhang, Yi Fang Shi, Geng Liang Zhu, Qu Cheng Liu, Qiu Ping Chen
  • Publication number: 20140339690
    Abstract: An integrated-circuit module includes an integrated-circuit device having a first surface and a plurality of bond pads disposed on the first surface. The module further includes metallic bond wires or metallic ribbons, which are attached between respective ones of a first subset of the bond pads and a package substrate or leadframe, such that a second subset of the bond pads are not attached to either a package substrate or leadframe. A metallic stud bump is affixed to each of one or more of the second subset of the bond pads. The integrated-circuit module further comprises a molding compound that contacts at least the first surface of the integrated-circuit device and substantially surrounds the bond wires or ribbon wires and the metallic stud bumps.
    Type: Application
    Filed: May 20, 2013
    Publication date: November 20, 2014
    Inventors: Swee Guan Chan, Kong Yang Leong, Mei Yong Wang, Heinrich Koerner
  • Patent number: 8397240
    Abstract: A method to handle peak database workloads may include requesting resources, receiving virtual-machine information in response to the requesting, allocating first and second portions of a workload according to the virtual-machine information, processing the first portion on a virtual machine to generate a first result, creating a cloned virtual machine with a virtualization layer, and cloning with the virtualization layer a storage allocated to the virtual machine to create a cloned storage.
    Type: Grant
    Filed: April 9, 2012
    Date of Patent: March 12, 2013
    Assignee: Dell Products, LP
    Inventors: Kong Yang, Ananda C. Sankaran
  • Publication number: 20120198450
    Abstract: A method to handle peak database workloads may include requesting resources, receiving virtual-machine information in response to the requesting, allocating first and second portions of a workload according to the virtual-machine information, processing the first portion on a virtual machine to generate a first result, creating a cloned virtual machine with a virtualization layer, and cloning with the virtualization layer a storage allocated to the virtual machine to create a cloned storage.
    Type: Application
    Filed: April 9, 2012
    Publication date: August 2, 2012
    Applicant: DELL PRODUCTS, LP
    Inventors: Kong Yang, Ananda C. Sankaran
  • Patent number: 8176497
    Abstract: A method to handle peak database workloads is disclosed. In one form of the disclosure, the method can include requesting resources, receiving virtual-machine information in response to requesting, and allocating first and second portions of a workload according to the virtual-machine information. The method can also include processing the first portion on a virtual machine to generate a first result, processing the second portion on a cloned virtual machine to generate a second result, and aggregating the first and the second results to form a response.
    Type: Grant
    Filed: January 16, 2008
    Date of Patent: May 8, 2012
    Assignee: Dell Products, LP
    Inventors: Kong Yang, Ananda C. Sankaran
  • Patent number: 7570081
    Abstract: An approach is provided in embodiments of the present invention for building multiple-output static CMOS logic gate circuits that share transistors when computing multiple functions from a common set of inputs. In particular, an approach is provided which includes building multiple-output static NAND gates that compute the subfunctions of three or more inputs and building multiple-output static NOR gates that compute the subfunctions of two or more inputs. The approach also includes building multiple-output static XOR-XNOR gates that are capable of computing two-input XOR, three-input XOR, two-input XNOR, and three-input XNOR, and building multiple-output static Propagate-Generate (PG) compound gates. The approach further includes building carry propagate adders, priority encoders, binary-to-thermometers, decoders, etc. that are capable of using the multiple-output static gates embodied in the present invention.
    Type: Grant
    Filed: August 30, 2006
    Date of Patent: August 4, 2009
    Assignee: Sun Microsystems, Inc.
    Inventors: David Money Harris, Chih-Kong Yang
  • Publication number: 20090183152
    Abstract: A method to handle peak database workloads is disclosed. In one form of the disclosure, the method can include requesting resources, receiving virtual-machine information in response to requesting, and allocating first and second portions of a workload according to the virtual-machine information. The method can also include processing the first portion on a virtual machine to generate a first result, processing the second portion on a cloned virtual machine to generate a second result, and aggregating the first and the second results to form a response.
    Type: Application
    Filed: January 16, 2008
    Publication date: July 16, 2009
    Applicant: DELL PRODUCTS, LP
    Inventors: Kong Yang, Ananda C. Sankaran
  • Publication number: 20060174228
    Abstract: A user may establish initial hardware pre-fetch and second sector pre-fetch settings, including threshold values and enables status for each. Based on a comparison of various metrics associated with processor performance and the threshold values, the enable status of hardware and/or second sector pre-fetching may be changed without requiring a system reboot (or processor reinitialization).
    Type: Application
    Filed: January 28, 2005
    Publication date: August 3, 2006
    Applicant: Dell Products L.P.
    Inventors: Ramesh Radhakrishnan, Kong Yang
  • Patent number: D1035754
    Type: Grant
    Filed: July 13, 2023
    Date of Patent: July 16, 2024
    Inventor: Kong Yang
  • Patent number: D1039190
    Type: Grant
    Filed: April 1, 2024
    Date of Patent: August 13, 2024
    Inventor: Kong Yang
  • Patent number: D1048535
    Type: Grant
    Filed: August 5, 2024
    Date of Patent: October 22, 2024
    Inventor: Kong Yang