Abstract: A memory controller of a memory system classifies input and output commands issued by a host into a group of read commands and a group of write commands, and manages the group of read commands and the group of write commands using first and second queues, respectively. The controller continuously processes a first group of commands among the group of read commands and the group of write commands until a first time period has elapsed from a start of the continuous processing of the first group of commands. In response to the first time period having elapsed, the controller switches a process target from the first group of commands to a second group of commands that is different from the first group of commands and selected among the group of read commands and the group of write commands.

Abstract: A memory system includes a first memory that is nonvolatile, a second memory that is volatile, and a memory controller. The memory controller is configured to store first information in the second memory. The first information includes management information. The memory controller is further configured to compress the first information. The compressed first information is second information. The memory controller is configured to store the second information in the first memory.

Abstract: A memory system, which is connectable to a host, includes a non-volatile memory and a controller configured to store data in the non-volatile memory and in a memory region within the host and read the data from the memory region within the host. The controller includes a first encoding/decoding circuit configured to execute encoding/decoding with a first encoding scheme, a second encoding/decoding circuit configured to execute encoding/decoding with a second encoding scheme having a higher error correcting capability than an error correcting capability of the first encoding scheme, an encoding scheme selecting circuit configured to select an encoding/decoding circuit from the first encoding/decoding circuit and the second encoding/decoding circuit to perform encoding of data to be stored in the memory region, based on information about the data read from the memory region.

Abstract: A memory system includes a first memory that is nonvolatile, a second memory that is volatile, and a memory controller. The memory controller is configured to store first information in the second memory. The first information includes management information. The memory controller is further configured to compress the first information. The compressed first information is second information. The memory controller is configured to store the second information in the first memory.

Abstract: According to one embodiment, a memory system includes a cache configured to cache a part of a multi-level mapping table for logical-to-physical address translation, and a controller. The multi-level mapping table includes a plurality of hierarchical tables corresponding to a plurality of hierarchical levels. The table of each hierarchical level includes a plurality of address translation data portions. The controller sets a priority for each of the hierarchical level based on a degree of bias of reference for each of the hierarchical level, and preferentially caches each of the address translation data portions of a hierarchical level with a high priority into the cache, over each of the address translation data portions of a hierarchical level with low priority.

Abstract: A memory system, which is connectable to a host, includes a non-volatile memory and a controller configured to store data in the non-volatile memory and in a memory region within the host and read the data from the memory region within the host. The controller includes a first encoding/decoding circuit configured to execute encoding/decoding with a first encoding scheme, a second encoding/decoding circuit configured to execute encoding/decoding with a second encoding scheme having a higher error correcting capability than an error correcting capability of the first encoding scheme, an encoding scheme selecting circuit configured to select an encoding/decoding circuit from the first encoding/decoding circuit and the second encoding/decoding circuit to perform encoding of data to be stored in the memory region, based on information about the data read from the memory region.

Abstract: A memory system, which is connectable to a host, includes a non-volatile memory and a controller configured to store data in the non-volatile memory and in a memory region within the host and read the data from the memory region within the host. The controller includes a first encoding/decoding circuit configured to execute encoding/decoding with a first encoding scheme, a second encoding/decoding circuit configured to execute encoding/decoding with a second encoding scheme having a higher error correcting capability than an error correcting capability of the first encoding scheme, an encoding scheme selecting circuit configured to select an encoding/decoding circuit from the first encoding/decoding circuit and the second encoding/decoding circuit to perform encoding of data to be stored in the memory region, based on information about the data read from the memory region.

Abstract: A storage device that can be connected to a host device includes a plurality of nonvolatile memories. Each nonvolatile memory includes first memory cells connected to a first word line and second memory cells connected to a second word line. The second word line is adjacent to the first word line. A method of operating the storage device includes maintaining parity data for the data that has been written to the first memory cells, and, upon detecting a failure in the writing of data to the second memory cells, restoring the data written to the first memory cells using the parity data.

Abstract: According to one embodiment, a memory system includes a cache configured to cache a part of a multi-level mapping table for logical-to-physical address translation, and a controller. The multi-level mapping table includes a plurality of hierarchical tables corresponding to a plurality of hierarchical levels. The table of each hierarchical level includes a plurality of address translation data portions. The controller sets a priority for each of the hierarchical level based on a degree of bias of reference for each of the hierarchical level, and preferentially caches each of the address translation data portions of a hierarchical level with a high priority into the cache, over each of the address translation data portions of a hierarchical level with low priority.

Abstract: A storage device that can be connected to a host device includes a plurality of nonvolatile memories. Each nonvolatile memory includes first memory cells connected to a first word line and second memory cells connected to a second word line. The second word line is adjacent to the first word line. A method of operating the storage device includes maintaining parity data for the data that has been written to the first memory cells, and, upon detecting a failure in the writing of data to the second memory cells, restoring the data written to the first memory cells using the parity data.

Abstract: A storage device that can be connected to a host device includes a plurality of nonvolatile memories. Each nonvolatile memory includes first memory cells connected to a first word line and second memory cells connected to a second word line. The second word line is adjacent to the first word line. A controller in the storage device is configured to maintain parity data in a memory area of the host device for the data that has been written to the first memory cells, and, upon detecting a failure in the writing of data to the second memory cells, restore the data written to the first memory cells using the parity data from the memory area of the host device.

Abstract: A memory system, which is connectable to a host, includes a non-volatile memory and a controller configured to store data in the non-volatile memory and in a memory region within the host and read the data from the memory region within the host. The controller includes a first encoding/decoding circuit configured to execute encoding/decoding with a first encoding scheme, a second encoding/decoding circuit configured to execute encoding/decoding with a second encoding scheme having a higher error correcting capability than an error correcting capability of the first encoding scheme, an encoding scheme selecting circuit configured to select an encoding/decoding circuit from the first encoding/decoding circuit and the second encoding/decoding circuit to perform encoding of data to be stored in the memory region, based on information about the data read from the memory region.

Abstract: A storage device includes a plurality of nonvolatile memories each of which includes first memory cells connected to a first word line and second memory cells connected to a second word line that is adjacent to the first word line, and a controller. The controller is configured to maintain parity data for data written in the first memory cells of the nonvolatile memories, and when carrying out data writing in the second memory cells connected to the second word line in a targeted nonvolatile memory, which is one of the plurality of nonvolatile memories, upon detecting a failure in the data writing therein, carrying out restoration of data that were written in the first memory cells of the targeted nonvolatile memory using the parity data.

Abstract: A storage device includes a plurality of nonvolatile memories each of which includes first memory cells connected to a first word line and second memory cells connected to a second word line that is adjacent to the first word line, and a controller. The controller is configured to maintain parity data for data written in the first memory cells of the nonvolatile memories, and when carrying out data writing in the second memory cells connected to the second word line in a targeted nonvolatile memory, which is one of the plurality of nonvolatile memories, upon detecting a failure in the data writing therein, carrying out restoration of data that were written in the first memory cells of the targeted nonvolatile memory using the parity data.

Abstract: A storage device that can be connected to a host device includes a plurality of nonvolatile memories. Each nonvolatile memory includes first memory cells connected to a first word line and second memory cells connected to a second word line. The second word line is adjacent to the first word line. A controller in the storage device is configured to maintain parity data in a memory area of the host device for the data that has been written to the first memory cells, and, upon detecting a failure in the writing of data to the second memory cells, restore the data written to the first memory cells using the parity data from the memory area of the host device.

Abstract: According to one embodiment, a memory system includes a nonvolatile memory, a device controller, and a tag memory. The device controller stores a part of a logical-to-physical address translation table (L2P table) stored in the nonvolatile memory in a memory of a host as a cache. The tag memory includes a plurality of entries associated with a plurality of cache lines of the cache. Each entry includes a tag indicating which area of the L2P table is stored in a corresponding cache line, and a plurality of bitmap flags indicating whether a plurality of sub-lines included in the corresponding cache line are valid or not.

Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller. The nonvolatile memory stores a multilevel address translation table including at least hierarchical first and second tables. The controller translates a logical address into a physical address by accessing a cache configured to cache both the first and second tables. The access range covered by each data portion of the second table is wider than the access range covered by each data portion of the first table. The controller preferentially evicts, from the cache, one of the cache lines which store the respective data portions of the first table.

Abstract: According to one embodiment, a memory system includes a nonvolatile memory, a device controller, and a tag memory. The device controller stores a part of a logical-to-physical address translation table (L2P table) stored in the nonvolatile memory in a memory of a host as a cache. The tag memory includes a plurality of entries associated with a plurality of cache lines of the cache. Each entry includes a tag indicating which area of the L2P table is stored in a corresponding cache line, and a plurality of bitmap flags indicating whether a plurality of sub-lines included in the corresponding cache line are valid or not.

Abstract: A device of one embodiment includes a host device including a first memory unit and host controller, and memory device. The host controller controls input/output accesses to the first memory unit. The memory device includes a nonvolatile semiconductor memory, second memory unit, protection circuit, and device controller. The second memory unit temporarily stores data to be transferred between the first memory unit and the nonvolatile semiconductor memory. The protection circuit protects data to be transferred from the second memory unit to the first memory unit by converting the data into an incomprehensible format. The device controller switches according to a control program whether or not to protect the data by the protection circuit.

Abstract: According to an embodiment of the invention, a memory device includes an interface unit, a determining unit, a second command generating unit, and a processor. The interface unit receives a first command from the outside of the memory device. The determining unit determines whether the first command received by the interface unit is an access command that is a write command or a read command. When the determining unit determines that the first command is the access command, the second command generating unit extracts access destination information, which is address information or size information of an access destination, from the first command and generates a second command which includes the extracted access destination information and has a size less than that of the first command. The processor executes the second command.