Abstract: A computer system comprising a plurality of caching agents with a cache hierarchy, the caching agents sharing memory across a system bus and issuing memory access requests in accordance with a protocol wherein a line of a cache has a present state comprising one of a plurality of line states. The plurality of line states includes a modified (M) state, wherein a line of a first caching agent in M state has data which is more recent than any other copy in the system; an exclusive (E) state, wherein a line in E state in a first caching agent is the only one of the agents in the system which has a copy of the data in a line of the cache, the first caching agent modifying the data in the cache line independent of other said agents coupled to the system bus; a shared (S) state, wherein a line in S state indicates that more than one of the agents has a copy of the data in the line; and an invalid (I) state indicating that the line does not exist in the cache.

Abstract: A memory subsystem and method for controlling an integrated circuit (IC) die with another IC die, and a computer system for use with the memory subsystem. The computer system uses a processor die to control the operation of a cache memory die. A dedicated interface is couple between the processor die and the auxiliary memory die to transfer information between the processor die and the auxiliary memory die. The processor die controls the auxiliary memory die using at least one micro-operation code transfer to the auxiliary memory die on a portion of the interface to specify at least one operation. The auxiliary memory die includes control logic that performs the operation and response to the micro-operation code. In this manner, the processor die controls the auxiliary memory die using the interface and the micro-operation code. The processor die and the cache memory die are contained in a single integrated circuit chip.

Abstract: An address translator and a method for translating a linear address into a physical address for memory management in a computer is described herein. Different memory sizes, and different page sizes can be selected. The address translator can translate from a standard 32-bit linear address for compatibility with previous 32-bit architectures, and can also translate to a physical memory size with a larger physical address than linear address; i.e., greater than 32 bits (e.g. 36 bits and up), with no increase in access time. The address translator translates a linear address that includes an offset and a plurality of fields used to select entries in a plurality of tables. The format of the linear address into fields is dependent upon the selected memory size and the selected page size.

Abstract: A method and apparatus of performing bus transactions on the bus of the computer system. The present invention includes a method and apparatus for permitting out-of-order replies in a pipelined bus system. The out-of-order responses include the sending of tokens between both the requesting agents and the responding agents in the computer system without the use of dedicated token buses.

Abstract: A system and method for providing a high performance symmetric arbitration protocol that includes support for priority agents. The bus arbitration protocol supports two classes of bus agents: symmetric agents and priority agents. The symmetric agents support fair, distributed arbitration using a round-robin algorithm. Each symmetric agent has a unique Agent ID assigned at reset. The algorithm arranges the symmetric agents in a circular order of priority. Each symmetric agent also maintains a bus ownership state of busy or idle and a Rotating ID that reflects the symmetric agent with the lowest priority in the next arbitration event. On an arbitration event, the symmetric agent with the highest priority becomes the symmetric owner. However, the symmetric owner is not necessarily the overall bus owner (i.e., a priority agent may be the overall bus owner).

Abstract: A method and apparatus of performing bus transactions on the external bus of the computer system. The present invention includes a method and apparatus for permitting out-of-order replies in a pipelined bus system. The out-of-order responses include the sending of tokens between both the requesting agents and the responding agents in the computer system without the use of dedicated token buses.

Abstract: A multi-level memory system is provided having a primary cache and a secondary cache in which unnecessary swapping operations are minimized. If a memory access request misses in the primary cache, but hits in the secondary cache, then the secondary cache responds to the request. If, however, the request also misses in the secondary cache, but is found in main memory, then main memory responds to the request. In responding to the request, the secondary cache or main memory returns the requested data to the primary cache. If an address tag of a primary cache victim line does not match an address tag in the secondary cache or the primary cache victim line is dirty, then the victim is stored in the secondary cache. The primary cache victim line includes a first bit for indicating whether the address tag of the primary cache victim line matches an address tag of the secondary cache.

Abstract: In a multi-processor system having a first processor, a second processor, and a bus coupling the first processor to the second processor, a method for correcting an erroneous signal corresponding to the first processor while maintaining lock atomicity. When an erroneous transaction is detected, the first processor aborts that transaction and performs a retry. On the retry, an arbitration process arbitrates between the first processor and the second processor to determine which processor is granted access to the bus. If an error is detected during the arbitration process, an arbitration re-synchronization process is initiated. In the arbitration re-synchronization process, bus requests are de-asserted and then re-arbitrated. In the re-arbitration process, the first processor initiates its request ahead of the other processor in order to maintain lock atomicity.

Abstract: A two-way set-associative cache memory includes both a set array and a data array in one embodiment. The data array comprises multiple elements, each of which can contain a cache line. The set array comprises multiple sets, with each set in the set array corresponding to an element in the data array. Each set in the set array contains information which indicates whether an address received by the cache memory matches the cache line contained in its corresponding element of the data array. The information stored in each set includes a tag and a state. The tag contains a reference to one of the cache lines in the data array. If the tag of a particular set matches the address received by the cache memory, then the cache line associated with that particular set is the requested cache line. The state of a particular set indicates the number of cache lines mapped into that particular set.

Abstract: An instruction locking apparatus and method for a cache memory allowing execution time predictability and high speed performance. The present invention implements a cache locking scheme in a two set associative instruction cache that utilizes a specially designed Least Recently Used (LRU) unit to effectively lock a first portion of the instruction cache to allow high speed and predictable execution time for time critical program code sections residing in the first portion while leaving another portion of the instruction cache free to operate as an instruction cache for other, non-critical, code sections. The present invention provides the above features in a system that is virtually transparent to the program code and does not require a variety of complex or specialized instructions or address coding methods. The present invention is flexible in that the two set associative instruction cache is transformed into what may be thought of as a static RAM in cache, and in addition, a direct map cache unit.

Abstract: A subsystem call mechanism for communicating between a first execution environment associated with a first domain object, and a second execution environment associated with a second domain object. An environment table object is associated with a process object. The environment table object includes a control stack which is an array of control stack entries which entries save the state of the first calling execution environment to be restored on a return from the second execution environment. A subsystem entry in the subsystem table specifies the object that defines region 2 of the target execution environment and the frame pointer of the topmost stack frame in the target environment, a supervisor Stack Pointer that is a linear address for the supervisor stack used when involving a supervisor call in the user mode (instead of the stack pointer in the current frame) to locate the new frame. The first domain object further includes Procedure Entries that specify the type and address of the target procedure.

Abstract: Access descriptors (24) include an object index (34) for selecting an object in the address space, and a rights field (35) specifying the permissible operations on a bi-paged object (38) selected by the access descriptor. An object table (42) has stored therein object descriptors for use in forming physical addresses to the page table directory object (60) which has page table descriptors stored therein for accessing page tables. A page table (44) has stored therein page table entries for use in forming physical addresses to the paged object (38). Logic compares the page rights field (81) of the page table entry with the rights field (62) of the page table descriptor in the page table directory entry and asserts a fault if the access permitted by the page rights field (50) is inconsistent with the rights field of the access descriptor in the page table directory entry.

Abstract: A tag bit is associated with each word stored in a memory. When the tag bit is a 0 the word is a data word and when a 1 the word is a valid access descriptor. Access descriptors include an object index for selecting an object in the address space of the memory, and a rights field specifying the permissible operations on a paged object selected by the access descriptor. An access descriptor in a processor control block contains a tag enable bit. An object table has stored therein object descriptors for use by an addressing mechanism in forming physical addresses to the page table object. The page table has stored therein page table entries for use by the addressing mechanism in forming physical addresses to the paged object. One of the access descriptors in a process control block contains an execution mode bit which represents either a user mode or a supervisor mode.

Abstract: An object-oriented computer architecture in which access descriptors include an object index for selecting an object in the address space, and a rights field specifying the permissible operations on a bi-paged object selected by the access descriptor. A local object lifetime bit is provided in the encoded fields portion of access descriptors, object descriptors, and page table entries to determine the lifetime of an object. The AD lifetime bit in the encoded fields of AD is compared in OTE Lifetime Check Logic with the destination object lifetime, the OTE local bit in the encoded fields of the OTE access descriptor. The OTE local bit in the encoded fields of the OTE is compared in PDTE Lifetime Check Logic with the destination object lifetime, the PDTE local bit in the encoded fields of the PDTE access descriptor.