Abstract: A method for the production of mask patterns for integrated semiconductor circuits composed of standard cells, such as gates, flip-flops, shift registers and the like, in which the cells are first grouped in a predeterminable number of cell groups in such a way that as few connections as possible extend between the groups and the space requirement of the individual groups is equal. Then, the cells forming a group are located in such a way that their wiring is possible upon as few wiring levels as possible so that the path of the connection lines is obtained and the resulting values are used for controlling an automatic drawing device for producing the mask patterns.