Abstract: In a time-division multiplexing system, data are supplied to the multiplexer with different speeds. Depending on the speed, time slot groups are allocated to the data, with the number of allocated time slots increasing with the speed. The search for groups of free time slots occurs in a fixed sequence. Data to which time slot groups at the end of the fixed sequence have been allocated, are relocated to time slot groups which have become free nearer the beginning of the sequence. The allocated time slot group for the forward transmission direction is signalled to the multiplexer of the remote station which in turn occasions a corresponding allocation of time slots for the reverse transmission direction for data originating at the remote station.

Abstract: A process for the transmission of data from a plurality of data sources utilizes a start-stop signal whose signal frame contains one code bit and data bits from a plurality of data sources between a start bit and a stop bit. Here, the code bits indicate the assignment of the data bits to the individual data sources.

Abstract: A process for testing a data transmission system by which data are transmitted by way of two data transmission links and by way of a first transmission device and a second transmission device provides that a test loop is closed, in dependence upon a loop signal, and a transmission section is tested. Data are transmitted in data blocks and each block includes a status bit, a synchronizing bit and n data bits. The loop signal is formed from a given combination of the status bit and data bits, and at least one of the data bits is inverted before being returned to the second transmission device.

Abstract: A process for T.D.M. frame synchronization which employs variable length synchronizing word at the receiving end and wherein the transmitter produces signals which consist of groups each comprising p bits and one marker bit and in respect to each multiplex frame contains a total of m marker bits of which s marker bits form the synchronizing words and where at the transmitter s-1 marker bits determine the following s-th marker bit and wherein the transmitted signal is stored and p+1 addresses are produced which are periodically assigned to the p bits and marker bits of each group and at the receiver the s-th bit is obtained from s-1 bits stored and compared with the corresponding received bit of the T.D.M. signal and when identity occurs pulses having a similar address are counted and a frame synchronizing signal is emitted.

Abstract: A circuit arrangement for facilitating the transmission of asynchronously occurring binary data values is described. According to prior art systems, each binary value change is assigned a multibit pulse group by means of channel units. These channel units require considerable technical complexity if a great many data sources are present. It is the principal object of the invention to replace the channel units by a centralized device. In accordance with the teachings of the invention, there are provided at the transmit and receive ends centralized coarse and fine time slot Raster counters and bit transition discriminators which process the pulse messages of all channels.

Abstract: A circuit arrangement for use in a time division multiplex (t.d.m.) data transmission system for lengthening the stop elements of data signals is described. The t.d.m. signals are transmitted via a transmission link to a receiver multiplexer. The outputs of the multiplexer are, respectively, connected by channel units to data sinks. Prior to reaching the multiplexer, however, the received data signals all pass through a central stop element lengthening device which produces a timing signal which is sequentially coupled to the channel units. The channel units, in the form of bistable stages, receive these timing signals and the information portions of the data signals, and from these establish the leading and trailing edges of the bits coupled to the respective data sinks.

Abstract: Apparatus is described for transmitting on a time division multiplex (t.d.m.) basis binary signals which are emitted by a plurality of data sources, each of which are connected to a multiplexer. During a cycle of operation the multiplexer establishes a conductive connection between each of its inputs, each of which is connected to a data source, and the output of the multiplexer for transmission to a receiver over a transmission link. Signals emitted from the multiplexer output are coupled to an in-phasing device which phases the individual bits into a t.d.m. signal.

Abstract: A switching arrangement is described for transmitting data in time division multiplex (TDM) systems on a character frame basis. The system includes a polarity reversal recognition circuit producing a polarity reversal signal and signaling polarity reversals of a data signal. A blocking circuit arrangement produces a stop signal thereby blocking the polarity reversal recognition circuit throughout the duration of a predetermined number of m bits of the data signal. A clock generator produces a clock signal which facilitates the sampling of the data signal. A shift register is provided which contains no fewer than m+2 cells and has a set of parallel input terminals for the parallel coupling of binary digits to the shift register. Serial input terminals to the shift register provide for the serial application of binary digits to the shift register. A clock pulse input terminal to the shift register receives shift register clock pulses.

Abstract: A switching arrangement for a data transmission system is described wherein the switching arrangement extends the receiver stop pulse length in time division multiplex transmissions of telegraph signals on a character frame basis. The character frame contains one start pulse, a number m code bits and one stop pulse. The time division multiplex (TDM) signal is applied to a first bistable circuit, and the output signal of the first bistable circuit is applied to a second bistable circuit from which a data signal is emitted to a data sink. A shift register is provided having no fewer than m+3 storage cells in which a first binary digit is stored if a stop signal is applied by means of parallel input terminals to the shift register. Timing pulses applied to the shift register are received in a pulse input. A shift register further includes a serial input terminal over which a second binary digit is read-in where no stop signal is present. A gate having inputs to which are applied the input signal of the m+3.sup.

Abstract: A method for transmitting data according to time division multiplex principles is described. In each multiplex frame synchronizing bits and data bits are transmitted from a multiplexer at the transmitter over a transmission device to a multiplexer at the receiver. In each time division multiplex frame a constant number of data bits are transmitted. The synchronism of the transmitter and receiver multiplexing devices and the transmission devices located at the transmitter and receiver are established by altering the duration of the time division multiplex frame.