Patents by Inventor Konstantin K. Bourdelle

Konstantin K. Bourdelle has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6930006
    Abstract: A semiconductor device having improved dielectric properties and a method for fabricating a semiconductor device. A semiconductor device includes a semiconductor layer suitable for device formation. A dielectric layer formed over the semiconductor layer has first and second opposing surfaces, a first surface region along the first surface and a second surface region along the second surface. A mid region is positioned between the first and second surface regions. The material of the dielectric layer includes a species having a concentration greater in the mid region than along the first opposing surface. The dielectric layer may be incorporated in a field effect transistor or a capacitor. According to a disclosed method an insulative layer is formed with two or more elements chemically bonded to one another. An additional species is introduced into the insulative layer in sufficient quantity to modify the net dielectric constant of the layer.
    Type: Grant
    Filed: May 13, 2002
    Date of Patent: August 16, 2005
    Assignee: Agere Systems Inc.
    Inventors: Konstantin K. Bourdelle, Yuanning Chen
  • Publication number: 20020163050
    Abstract: A semiconductor device having improved dielectric properties and a method for fabricating a semiconductor device. A semiconductor device includes a semiconductor layer suitable for device formation. A dielectric layer formed over the semiconductor layer has first and second opposing surfaces, a first surface region along the first surface and a second surface region along the second surface. A mid region is positioned between the first and second surface regions. The material of the dielectric layer includes a species having a concentration greater in the mid region than along the first opposing surface. The dielectric layer may be incorporated in a field effect transistor or a capacitor. According to a disclosed method an insulative layer is formed with two or more elements chemically bonded to one another. An additional species is introduced into the insulative layer in sufficient quantity to modify the net dielectric constant of the layer.
    Type: Application
    Filed: May 13, 2002
    Publication date: November 7, 2002
    Inventors: Konstantin K. Bourdelle, Yuanning Chen
  • Patent number: 6306780
    Abstract: A method for making a photoresist layer includes forming a photoresist layer adjacent a substrate and patterning the photoresist layer. The photoresist layer may include at least one of a solvent and water. The photoresist layer may then be heated and exposed to ultraviolet light during the heating to reduce at least one of the solvent and water therein. As a result, the formation of gases in the photoresist layer during ion implantation is reduced, which thus reduces damage to the photoresist layer from blistering, peeling, lifting, or reticulation, for example. The photoresist layer may be formed to have a thickness greater than about 2 &mgr;m, for example, to block high-current, high-dosage, high-energy ion implantation. Exposing may include exposing the photoresist layer to ultraviolet light having a power density in a range of about 200 to 500 mW/cm2, and, more preferably, about 270 to 360 mW/cm2, and having a wavelength in a range of about 200 to 300 nm, for example.
    Type: Grant
    Filed: October 26, 2000
    Date of Patent: October 23, 2001
    Assignee: Agere Systems Guardian Corp.
    Inventors: Konstantin K. Bourdelle, Pradip Kumar Roy
  • Patent number: 6136672
    Abstract: A process for semiconductor device fabrication in which a Czochralski silicon substrate is implanted with boron is disclosed. The boron is implanted using an energy of about 500 keV to about 3 MeV and a dose of about 3.times.10.sup.13 /cm.sup.2 to about 3.times.10.sup.14 /cm.sup.2. In order to reduce the threading dislocation density in the substrate to less than about 10.sup.3 /cm.sup.2 at a depth in the substrate of at least about 0.5 .mu.m, after the implant, the substrate is annealed in a two-step process. First the substrate is annealed at a temperature in the range of about 725.degree. C. to about 775.degree. C. followed by an anneal at a temperature of at least about 900.degree. C. The duration of the first step is selected to provide a dislocation density of less than about 10.sup.3 /cm.sup.2 at the desired depth in the substrate.
    Type: Grant
    Filed: August 10, 1998
    Date of Patent: October 24, 2000
    Assignee: Lucent Technologies Inc.
    Inventors: Konstantin K. Bourdelle, David James Eaglesham