Patents by Inventor Konstantine Karavakis
Konstantine Karavakis has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6465878Abstract: A microelectronic assembly includes a microelectronic element having a first surface including a central region and a peripheral region surrounding the central region, the microelectronic element including a plurality of contacts disposed in the central region. The microelectronic assembly also includes a compliant layer over the peripheral region of the first surface, the compliant layer having a bottom surface facing toward the first surface of the microelectronic element, a top surface facing upwardly away from the microelectronic element and one or more edge surfaces extending between the top and bottom surfaces. A plurality of flexible bond ribbons are disposed over the compliant layer so that the bond ribbons extend over the top surface and one or more of the edge surfaces and the bond ribbons electrically connect the contacts to conductive terminals overlying the top surface of the compliant layer.Type: GrantFiled: February 6, 2001Date of Patent: October 15, 2002Assignee: Tessera, Inc.Inventors: Joseph Fjelstad, Konstantine Karavakis
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Publication number: 20020117329Abstract: A connection component for making connections to a microelectronic element is made by providing leads on a surface of a polymeric layer and etching the polymeric layer to partially detach the leads from the polymeric layer, leaving a portion of each lead releasably connected to the polymeric layer by a small polymeric connecting element which can be broken or peeled away from the lead. Leads in a connecting element may be covered by an insulating jacket applied by a coating process, and the insulating jacket may in turn be covered by a conductive layer so that each lead becomes a miniature coaxial cable. This arrangement provides immunity to interference and facilitates operation at high speeds.Type: ApplicationFiled: January 28, 2002Publication date: August 29, 2002Inventors: Belgacem Haba, Konstantine Karavakis
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Publication number: 20020115236Abstract: A compliant semiconductor chip package with fan-in leads and a method for manufacturing the same. The package, or “assembly”, contains a multiplicity of bond ribbons connected between the contacts of a semiconductor chip and corresponding terminals on a top surface of a compliant layer. The compliant layer provides stress relief to the bond ribbons encountered during handling or affixing the assembly to an external substrate. The chip package also contains a dielectric layer adjacent to at least one end of the bond ribbons. The dielectric layer relieves mechanical stresses associated with the thermal mismatch of assembly and substrate materials during thermal cycling. The assembly can be manufactured without the need for any bond wiring tools once the bond ribbons are patterned and formed during a standard photolithographic stage within the manufacturing process.Type: ApplicationFiled: February 9, 1998Publication date: August 22, 2002Inventors: JOSEPH FJELSTAD, KONSTANTINE KARAVAKIS
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Publication number: 20020100961Abstract: A microelectronic assembly includes a microelectronic element having a first surface with a plurality of contacts accessible at the first surface, and a compliant layer over the first surface of the microelectronic element, the compliant layer including a plurality of bumped protrusions and openings adjacent the bumped protrusions for providing access to the contacts, wherein each bumped protrusion includes a top surface and at least one sloping edge. The microelectronic assembly also includes conductive terminals over the top surfaces of the bumped protrusions, and a plurality of conductive bond ribbons having first ends in engagement with the contacts, second ends in engagement with the terminals and intermediate sections extending along the sloping edges for electrically interconnecting the contacts and the terminals.Type: ApplicationFiled: March 26, 2002Publication date: August 1, 2002Inventors: Joseph Fjelstad, Konstantine Karavakis
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Patent number: 6423907Abstract: A connection component for making connections to a microelectronic element is made by providing leads on a surface of a polymeric layer and etching the polymeric layer to partially detach the leads from the polymeric layer, leaving a portion of each lead releasably connected to the polymeric layer by a small polymeric connecting element which can be broken or peeled away from the lead. Leads in a connecting element may be covered by an insulating jacket applied by a coating process, and the insulating jacket may in turn be covered by a conductive layer so that each lead becomes a miniature coaxial cable. This arrangement provides immunity to interference and facilitates operation at high speeds.Type: GrantFiled: April 14, 2000Date of Patent: July 23, 2002Assignee: Tessera, Inc.Inventors: Belgacem Haba, Konstantine Karavakis
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Publication number: 20020081781Abstract: A connection component for use in making microelectronic element assemblies which has peelable leads that are formed on a dielectric support structure. One end of each lead is permanently connected to the support structure and the opposite end of the lead is releasably connected to the support structure. When the releasable end of the lead is bonded to a contact on a semiconductor chip, the releasable end of the lead can be peeled from the support structure such that the chip may be moved away from the support structure. A compliant layer may be disposed between the chip and the support structure. If a compliant material is injected between the chip and the support structure to form the compliant layer, the compliant material will lift the chip away from the support structure and facilitate the peeling of the leads from the support structure.Type: ApplicationFiled: December 28, 2001Publication date: June 27, 2002Inventors: Thomas H. DiStefano, Joseph Fjelstad, Belgacem Haba, Owais Jamil, Konstantine Karavakis, David Light, John W. Smith
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Patent number: 6373128Abstract: A semiconductor chip assembly with a compliant layer overlying the chip and a flexible dielectric layer overlying the compliant layer. Connecting terminals are provided on the dielectric layer for connection to a larger substrate. The connecting terminals are moveable in vertical directions toward the chip. Bonding terminals, electrically connected to the connecting terminals, are also provided on the top layer. A reinforcing element resists vertical movement of the bonding terminals, and thereby facilitates connection of leads between the bonding terminals and the chip.Type: GrantFiled: November 27, 2000Date of Patent: April 16, 2002Assignee: Tessera, Inc.Inventors: Konstantine Karavakis, Joseph Fjelstad
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Patent number: 6370032Abstract: The present invention provides an interconnection scheme having complaint contacts arranged in an array to connect conductive surfaces on a microelectronic device and a supporting substrate, such as a printed circuit board. This invention accommodates for the difference in thermal coefficients of expansion between the device and the supporting substrate. Typically, an area array of conductive contact pads are connected into rows by conductive leads on a flexible, intermediate substrate. Each of the conductive leads bridges a bonding hole in the intermediate substrate which is situated between successive contact pads. Each of the conductive leads further has a frangible portion within or near each bonding hole. A stand-off between the intermediate substrate and the device is create by compliant dielectric pads, typically composed of an elastomer material, positioned under each contact pad.Type: GrantFiled: September 17, 1999Date of Patent: April 9, 2002Assignee: Tessera, Inc.Inventors: Thomas H. DiStefano, John W. Smith, Zlata Kovac, Konstantine Karavakis
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Patent number: 6357112Abstract: A connection component for use in making microelectronic element assemblies, has peelable leads that are formed on a dielectric support structure. One end of each lead is permanently connected to the support structure and the opposite end of the lead is releasably connected to the support structure. When the releasable end of the lead is bonded to a contact on a semiconductor chip, the releasable end of the lead can be peeled from the support structure such that the chip may be moved away from the support structure. A compliant layer may be disposed between the chip and the support structure. If a compliant material is injected between the chip and the support structure to form the compliant layer, the compliant material will lift the chip away from the support structure and facilitate the peeling of the leads from the support structure.Type: GrantFiled: November 25, 1998Date of Patent: March 19, 2002Assignee: Tessera, Inc.Inventors: Thomas H. DiStefano, Joseph Fjelstad, Belgacem Haba, Owais Jamil, Konstantine Karavakis, David Light, John W. Smith
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Patent number: 6274822Abstract: A semiconductor chip connection component having numerous leads extending side-by-side across a gap in a support structure, each lead having a frangible section to permit detachment of one end of the lead from the support structure in a bonding process. The frangible sections are formed by treating the lead-forming material in an elongated treatment zone extending across the regions occupied by numerous leads to provide a step defining a fracture point of the lead during a wire bonding process.Type: GrantFiled: July 2, 1998Date of Patent: August 14, 2001Assignee: Tessera, Inc.Inventors: David Light, Belgacem Haba, Thomas H. Distefano, Konstantine Karavakis
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Publication number: 20010007375Abstract: A microelectronic assembly includes a microelectronic element having a first surface including a central region and a peripheral region surrounding the central region, the microelectronic element including a plurality of contacts disposed in the central region. The microelectronic assembly also includes a compliant layer over the peripheral region of the first surface, the compliant layer having a bottom surface facing toward the first surface of the microelectronic element, a top surface facing upwardly away from the microelectronic element and one or more edge surfaces extending between the top and bottom surfaces. A plurality of flexible bond ribbons are disposed over the compliant layer so that the bond ribbons extend over the top surface and one or more of the edge surfaces and the bond ribbons electrically connect the contacts to conductive terminals overlying the top surface of the compliant layer.Type: ApplicationFiled: February 6, 2001Publication date: July 12, 2001Inventors: Joseph Fjelstad, Konstantine Karavakis
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Patent number: 6215191Abstract: A method of treating a lead in a chip package. A conductive lead is positioned such that it extends across a gap in a dielectric substrate and is secured at either end to a first surface of the substrate. Directed energy is then applied to a desired portion of the surface of the lead within the gap. As a result of the application of energy, a surface layer of the lead is recrystallized thereby creating a fine grain, dense surface layer of lead material. Surface contaminates may be vaporized and contaminants at the grain boundaries of the recrystallized surface layers may be driven away from the grain boundaries such that a treated lead is more ductile and has better resistance to thermal cycling after the lead has been attached to a chip contact.Type: GrantFiled: March 30, 1999Date of Patent: April 10, 2001Assignee: Tessera, Inc.Inventors: Masud Beroz, Konstantine Karavakis, Thomas H. DiStefano
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Patent number: 6211572Abstract: A compliant semiconductor chip package with fan-in leads and a method for manufacturing the same. The package, or “assembly”, contains a multiplicity of bond ribbons connected between the contacts of a semiconductor chip and corresponding terminals on a top surface of a compliant layer. The compliant layer provides stress relief to the bond ribbons encountered during handling or affixing the assembly to an external substrate. The chip package also contains a dielectric layer adjacent to at least one end of the bond ribbons. The dielectric layer relieves mechanical stresses associated with the thermal mismatch of assembly and substrate materials during thermal cycling. The assembly can be manufactured without the need for any bond wiring tools since the bond ribbons are patterned and formed during a standard photolithographic stage within the manufacturing process.Type: GrantFiled: October 29, 1996Date of Patent: April 3, 2001Assignee: Tessera, Inc.Inventors: Joseph Fjelstad, Konstantine Karavakis
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Patent number: 6204455Abstract: A microelectronic element assembly such as a semiconductor chip assembly uses a connection component incorporating a dielectric sheet with electrically conductive elements therein. Each electrically conductive element may include a flexible shell. The flexible shells can be formed to assure reliable engagement with mating contact pads.Type: GrantFiled: June 30, 1999Date of Patent: March 20, 2001Assignee: Tessera, Inc.Inventors: Kenneth B. Gilleo, Konstantine Karavakis
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Patent number: 6157075Abstract: A semiconductor chip assembly with a compliant layer overlying the chip and a flexible dielectric layer overlying the compliant layer. Connecting terminals are provided on the dielectric layer for connection to a larger substrate. The connecting terminals are moveable in vertical directions toward the chip. Bonding terminals, electrically connected to the connecting terminals, are also provided on the top layer. A reinforcing element resists vertical movement of the bonding terminals, and thereby facilitates connection of leads between the bonding terminals and the chip.Type: GrantFiled: August 27, 1999Date of Patent: December 5, 2000Assignee: Tessera, Inc.Inventors: Konstantine Karavakis, Joseph Fjelstad
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Patent number: 6086386Abstract: A connector for microelectronic elements includes a sheetlike body having a plurality of active contacts arranged in a regular grid pattern. The active contacts may include several sheetlike metallic projections extending inwardly around a hole in the sheetlike element, on a first major surface of the sheetlike element. A support structure such as a grid array of noncollapsing structural posts is on a second major surface of the sheetlike element, and each of the posts is electrically connected to one of the active contacts. The grid array of posts and the grid array of active contacts are offset from one another so that an active contact is surrounded by several posts. The posts support the sheetlike element spaced away from a substrate to which the posts are attached. A microelectronic element having bump leads thereon may be engaged by contacting the bump leads with the active contacts, and deflecting the sheetlike element between the bump leads on one side and the posts on the other side.Type: GrantFiled: May 22, 1997Date of Patent: July 11, 2000Assignee: Tessera, Inc.Inventors: Joseph Fjelstad, Thomas H. DiStefano, Konstantine Karavakis, Anthony B. Faraci, Tan Nguyen
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Patent number: 6012224Abstract: The present invention provides an interconnection scheme having compliant contacts arranged in an array to connect conductive surfaces on a microelectronic device and a supporting substrate, such as a printed circuit board. This invention accommodates for the difference in thermal coefficients of expansion between the device and the supporting substrate. Typically, an area array of conductive contact pads are connected into rows by conductive leads on a flexible, intermediate substrate. Each of the conductive leads bridges a bonding hole in the intermediate substrate which is situated between successive contact pads. Each of the conductive leads further has a frangible portion within or near each bonding hole. A stand-off between the intermediate substrate and the device is create by compliant dielectric pads, typically composed of an elastomer material, positioned under each contact pad.Type: GrantFiled: September 25, 1997Date of Patent: January 11, 2000Assignee: Tessera, Inc.Inventors: Thomas H. DiStefano, John W. Smith, Zlata Kovac, Konstantine Karavakis
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Patent number: 5971253Abstract: A microelectronic element assembly such as a semiconductor chip assembly uses a connection component incorporating a dielectric sheet with electrically conductive elements therein. Each electrically conductive element may include a flexible shell. The flexible shells can be formed to assure reliable engagement with mating contact pads.Type: GrantFiled: December 27, 1996Date of Patent: October 26, 1999Assignee: Tessera, Inc.Inventors: Kenneth B. Gilleo, Konstantine Karavakis
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Patent number: 5966592Abstract: A method of treating a lead in a chip package. A conductive lead is positioned such that it extends across a gap in a dielectric substrate and is secured at either end to a first surface of the substrate. Directed energy is then applied to a desired portion of the surface of the lead within the gap. As a result of the application of energy, a surface layer of the lead is recrystallized thereby creating a fine grain, dense surface layer of lead material. Surface contaminates may be vaporized and contaminants at the grain boundaries of the recrystallized surface layers may be driven away from the grain boundaries such that a treated lead is more ductile and has better resistance to thermal cycling after the lead has been attached to a chip contact.Type: GrantFiled: November 21, 1995Date of Patent: October 12, 1999Assignee: Tessera, Inc.Inventors: Masud Beroz, Konstantine Karavakis, Thomas H. Distefano
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Patent number: 5966587Abstract: A method of forming a microelectronic assembly having an element with contacts on a front surface thereof, an interposer with a plurality of connecting terminals in a connecting terminal region and bonding terminals in a bonding terminal region electrically connected to the connecting terminals includes the steps of juxtaposing the interposer with the microelectronic element so that the connecting terminals and bonding terminals of the interposer face away from the front surface of the element and so that the bonding terminal region is adjacent to the contacts of the microelectronic element; and connecting at least some of the contacts with at least some of the bonding terminals by a plurality of flexible leads while supporting the bonding terminals against the vertical movement to facilitate the connection.Type: GrantFiled: February 9, 1998Date of Patent: October 12, 1999Assignee: Tessera, Inc.Inventors: Konstantine Karavakis, Joseph Fjelstad