Abstract: The present disclosure concerns a RF transceiver (100) comprising: a single RF antenna port (20) for a receive path, a first transmit path and a second transmit path a balun (10) comprising a primary winding (11) and a secondary winding (12), wherein a first terminal of the secondary winding (12) is coupled to the RF antenna port (20), the receive path, which comprises a low noise amplifier (LNA), comprising an input terminal coupled to a second terminal of the secondary winding (12), the first transmit path, which comprises a high power amplifier (HPA), comprising differential output terminals (3, 4) coupled to the primary winding (11), and a first and second switches (S1, S2), a third capacitor (C1), a fourth capacitor (C2), the second transmit path, which comprises a low power amplifier (LPA), and a third switch (S3).

Abstract: Methods form amplifier device structures that include first-third amplifier devices. The first amplifier device produces an intermediate signal. The second amplifier device is connected to an input of the first amplifier device and produces an amplified inverted output signal. The third amplifier device inverts the intermediate signal to produce an amplified non-inverted output signal that is complementary to the amplified inverted output signal. A resistor feedback loop is connected to the input and output of the first amplifier device. A gain ratio of the gain of the third amplifier device to the gain of the second amplifier device matches a resistance ratio of the source resistance of the input signal to the resistance of the resistor added to the source resistance. Also, DC loop circuits are connected to the first-third amplifier devices, and each of the DC loop circuits connects an amplifier device output to an amplifier device input.

Abstract: Embodiments described herein provide circuitry employing an inductor having enhanced circuit area usage. The circuitry includes an inductor having a first loop and a second loop adjoining the first loop to form a figure-eight configuration. The circuitry further includes a circuit component disposed at least partially inside an area defined by at least one of the first loop and the second loop. The inductor has an intersection portion between the first loop and the second loop. An input node is located proximate to the intersection portion, the input node having a first extension disposed inside the first loop. An output node is located proximate to the intersection portion. The output node has a second extension disposed inside the second loop. At least a first capacitor is coupled to the input node and the second extension, and at least a second capacitor coupled to the output node and the first extension.

Abstract: Methods form amplifier device structures that include first-third amplifier devices. The first amplifier device produces an intermediate signal. The second amplifier device is connected to an input of the first amplifier device and produces an amplified inverted output signal. The third amplifier device inverts the intermediate signal to produce an amplified non-inverted output signal that is complementary to the amplified inverted output signal. A resistor feedback loop is connected to the input and output of the first amplifier device. A gain ratio of the gain of the third amplifier device to the gain of the second amplifier device matches a resistance ratio of the source resistance of the input signal to the resistance of the resistor added to the source resistance. Also, DC loop circuits are connected to the first-third amplifier devices, and each of the DC loop circuits connects an amplifier device output to an amplifier device input.

Abstract: A circuit comprises an oscillator including a differential tank circuit, an oscillator carrier, and an active device. A phase difference between the oscillator carrier and a device current of the active device is adjusted to reduce upconversion of flicker noise of the oscillator. The circuit includes a common-mode reactance circuit configured to provide an intentionally introduced common-mode inductance, common-mode capacitance, or both, The common-mode reactance circuit is configured to adjust at common-mode impedance of the oscillator. A method comprises adjusting a phase difference between an oscillator carrier of an oscillator and a device current of an active device of the oscillator. The adjusted phase difference is selected to reduce upconversion of flicker noise generated in the oscillator. Adjusting the phase difference includes adjusting a common-mode impedance of the oscillator.

Abstract: A power amplifier circuit, comprising: a final stage, comprising first and second amplifying elements for amplifying an input signal; and a driver stage, for providing the input signal to the final stage. The circuit is characterized by a first capacitor coupled between an input of the first amplifying element and an output of the second amplifying element; and a second capacitor coupled between an input of the second amplifying element and an output of the first amplifying element.

Abstract: A circuit for amplifying the power of signal, the circuit comprising a power amplifier, a transformer and a load; wherein the transformer comprises a primary inductor and a secondary inductor, the first inductor being coupled to, and capable of being driven by, the power amplifier, and the secondary inductor coupled to, and capable of driving, the load; wherein a first one of the primary and secondary inductors is a variable inductor whose inductance is variable responsive to a control input in order to change the output power of the amplifier.

Abstract: A power amplifier circuit, comprising: an amplifier for receiving an input signal to be amplified; a power input for coupling the amplifier to a power supply; and a transformer for providing the amplified signal from the amplifier to a load, comprising a primary inductor and a secondary inductor. The power amplifier circuit is characterized by: a first capacitor coupled in parallel with the primary inductor; and a second capacitor coupled in parallel with the secondary inductor; wherein at least one of the first and second capacitors has a variable capacitance.

Abstract: A circuit for amplifying the power of signal, the circuit comprising a power amplifier, a transformer and a load; wherein the transformer comprises a primary inductor and a secondary inductor, the first inductor being coupled to, and capable of being driven by, the power amplifier, and the secondary inductor coupled to, and capable of driving, the load; wherein a first one of the primary and secondary inductors is a variable inductor whose inductance is variable responsive to a control input in order to change the output power of the amplifier.

Abstract: A power amplifier circuit, comprising: an amplifier for receiving an input signal to be amplified; a power input for coupling the amplifier to a power supply; and a transformer for providing the amplified signal from the amplifier to a load, comprising a primary inductor and a secondary inductor. The power amplifier circuit is characterized by: a first capacitor coupled in parallel with the primary inductor; and a second capacitor coupled in parallel with the secondary inductor; wherein at least one of the first and second capacitors has a variable capacitance.

Abstract: A power amplifier circuit, comprising: an input for receiving an input signal to be amplified; a power supply; an amplifier, coupled to the input and the power supply; and a cascode device coupled between the power supply and the amplifier. The circuit is characterized by: a first current source coupled between the input and the amplifier, configured to provide a biasing current which is proportional to absolute temperature; and a second current source for controlling the cascode device, configured to provide a current which is complementary to absolute temperature (CTAT).

Abstract: A power amplifier circuit, comprising: a final stage, comprising first and second amplifying elements for amplifying an input signal; and a driver stage, for providing the input signal to the final stage. The circuit is characterized by a first capacitor coupled between an input of the first amplifying element and an output of the second amplifying element; and a second capacitor coupled between an input of the second amplifying element and an output of the first amplifying element.

Abstract: A power amplifier circuit, comprising: an input for receiving an input signal to be amplified; a power supply; an amplifier, coupled to the input and the power supply; and a cascode device coupled between the power supply and the amplifier. The circuit is characterized by: a first current source coupled between the input and the amplifier, configured to provide a biasing current which is proportional to absolute temperature; and a second current source for controlling the cascode device, configured to provide a current which is complementary to absolute temperature (CTAT).

Abstract: A receiver comprising: an antenna for receiving signals in a plurality of frequency bands; an integrated circuit including a plurality of amplifiers, wherein each of the plurality of amplifiers is configured to amplify signals in one of the plurality of frequency bands; and a plurality of selectable receive paths, each of the plurality of selectable receive paths connecting an output of the antenna to an input of one of the plurality of amplifiers and including a resonant circuit.

Abstract: A receiver comprising: an antenna for receiving signals in a plurality of frequency bands; an integrated circuit including a plurality of amplifiers, wherein each of the plurality of amplifiers is configured to amplify signals in one of the plurality of frequency bands; and a plurality of selectable receive paths, each of the plurality of selectable receive paths connecting an output of the antenna to an input of one of the plurality of amplifiers and including a resonant circuit.

Abstract: A charge pumped phase locked loop circuit (PLL) is disclosed that includes a phase detector for detecting the phase error between a reference clock and an output clock to generate a phase error signal. A charge pump is provided that is controlled by the phase error signal to either source current to an intermediate control node or to sink current therefrom. An isolation circuit maintains the intermediate control node at a virtual AC reference voltage such that it remains at substantially the same voltage during the sourcing of current thereto or sinking of current therefrom, the isolation circuit generating a control voltage on the output thereof to control the frequency of the output clock. A loop filter is provided for filtering the control voltage.

Abstract: An integrated high frequency inductor is disclosed that includes first and second conductor loops. The first conductor loop is fabricated in a conductive layer of a semiconductor substrate and having a first substantially constant width. The second conductor loop is fabricated in the conductive layer and within the boundary of the first conductor loop and having a second substantially constant width less than the first substantially constant width, and the outer perimeter of the second conductor loop separated from the inner perimeter of the first conductor loop by a substantially constant gap. A first conductor bridge connects a first end of the first conductor loop to a first end of the second conductor loop.

Abstract: A charge pumped phase locked loop circuit (PLL) is disclosed that includes a phase detector for detecting the phase error between a reference clock and an output clock to generate a phase error signal. A charge pump is provided that is controlled by the phase error signal to either source current to an intermediate control node or to sink current therefrom. An isolation circuit maintains the intermediate control node at a virtual AC reference voltage such that it remains at substantially the same voltage during the sourcing of current thereto or sinking of current therefrom, the isolation circuit generating a control voltage on the output thereof to control the frequency of the output clock. A loop filter is provided for filtering the control voltage.

Abstract: A programmable, rail-to-rail, low-voltage, micro-power harmonic-mean class-AB output stage with MOS devices employed in weak inversion is provided. The output stage MOS devices are arranged in the translinear loop, which avoids having a plurality of MOS devices in series between the power supply rails and thus enables low-voltage operation. The MOS devices in the translinear loop are used to implement the harmonic mean function x*y=z*(x+y) where x and y are mirrored to the output and represent the quiescent push and pull currents, respectively. Circuit operational parameters may be varied to suit a variety of different applications. Increasing the supply voltage for given quiescent current will advantageously increase the maximum current load. Increasing the quiescent current for given supply voltage will advantageously lower the distortion of the output stage.

Abstract: A programmable, rail-to-rail, low-voltage, micro-power harmonic-mean class-AB output stage with MOS devices employed in weak inversion is provided. The output stage MOS devices are arranged in the translinear loop, which avoids having a plurality of MOS devices in series between the power supply rails and thus enables low-voltage operation. The MOS devices in the translinear loop are used to implement the harmonic mean function x*y=z*(x+y) where x and y are mirrored to the output and represent the quiescent push and pull currents, respectively. Circuit operational parameters may be varied to suit a variety of different applications. Increasing the supply voltage for given quiescent current will advantageously increase the maximum current load. Increasing the quiescent current for given supply voltage will advantageously lower the distortion of the output stage.