Patents by Inventor Konstantinos Papamichael
Konstantinos Papamichael has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230379254Abstract: Techniques and algorithms for monitoring network congestion and for triggering a flow to follow a new path through a network. The network is monitored, and network feedback data is acquired, where that data indicates whether the network is congested. If the network is congested, a feedback-driven algorithm can trigger a flow to follow a new path. By triggering the flow to follow the new path, congestion in the network is reduced. To identify congestion, the feedback data is analyzed to determine whether flows are colliding. The feedback-driven algorithm determines that a network remapping event is to occur in an attempt to alleviate the congestion. A flow is then selected to be remapped to alleviate the congestion.Type: ApplicationFiled: May 18, 2022Publication date: November 23, 2023Inventors: Michael Konstantinos PAPAMICHAEL, Mohammad Saifee DOHADWALA, Adrian Michael CAULFIELD, Prashant RANJAN
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Publication number: 20210392210Abstract: A masked packet checksum is utilized to provide error detection and/or error correction for only discrete portions of a packet, to the exclusion of other portions, thereby avoiding retransmission if transmission errors appear only in portions excluded by the masked packet checksum. A bitmask identifies packet portions whose data is to be protected with error detection and/or error correction schemes, packet portions whose data is to be excluded from such error detection and/or error correction schemes, or combinations thereof. A bitmask can be a per-packet specification, incorporated into one or more fields of individual packets, or a single bitmask can apply equally to multiple packets, which can be delineated in numerous ways, and can be separately transmitted or derived. Bitmasks can be generated at higher layers with lower layer mechanisms deactivated, or can be generated lower layers based upon data passed down.Type: ApplicationFiled: August 30, 2021Publication date: December 16, 2021Inventors: Adrian Michael CAULFIELD, Michael Konstantinos PAPAMICHAEL
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Patent number: 11108894Abstract: A masked packet checksum is utilized to provide error detection and/or error correction for only discrete portions of a packet, to the exclusion of other portions, thereby avoiding retransmission if transmission errors appear only in portions excluded by the masked packet checksum. A bitmask identifies packet portions whose data is to be protected with error detection and/or error correction schemes, packet portions whose data is to be excluded from such error detection and/or error correction schemes, or combinations thereof. A bitmask can be a per-packet specification, incorporated into one or more fields of individual packets, or a single bitmask can apply equally to multiple packets, which can be delineated in numerous ways, and can be separately transmitted or derived. Bitmasks can be generated at higher layers with lower layer mechanisms deactivated, or can be generated lower layers based upon data passed down.Type: GrantFiled: August 9, 2019Date of Patent: August 31, 2021Assignee: Microsoft Technology Licensing, LLCInventors: Adrian Michael Caulfield, Michael Konstantinos Papamichael
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Patent number: 11068412Abstract: Techniques are disclosed for implementing direct memory access in a virtualized computing environment. A new mapping of interfaces between RNIC Consumer and RDMA Transport is defined, which enables efficient retry, a zombie detection mechanism, and identification and handling of invalid requests without bringing down the RDMA connection. Techniques are disclosed for out of order placement and delivery of ULP Requests without constraining the RNIC Consumer to the ordered networking behavior, if it is not required for the ULP (e.g., storage). This allows efficient deployment of an RDMA accelerated storage workload in a lossy network configuration, and reduction in latency jitter.Type: GrantFiled: February 22, 2019Date of Patent: July 20, 2021Assignee: Microsoft Technology Licensing, LLCInventors: Matthew Graham Humphrey, Vadim Makhervaks, Michael Konstantinos Papamichael
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Patent number: 11025564Abstract: Techniques are disclosed for implementing direct memory access in a virtualized computing environment. A new mapping of interfaces between RNIC Consumer and RDMA Transport is defined, which enables efficient retry, a zombie detection mechanism, and identification and handling of invalid requests without bringing down the RDMA connection. Techniques are disclosed for out of order placement and delivery of ULP Requests without constraining the RNIC Consumer to the ordered networking behavior, if it is not required for the ULP (e.g., storage). This allows efficient deployment of an RDMA accelerated storage workload in a lossy network configuration, and reduction in latency jitter.Type: GrantFiled: February 22, 2019Date of Patent: June 1, 2021Assignee: Microsoft Technology Licensing, LLCInventors: Matthew Graham Humphrey, Vadim Makhervaks, Michael Konstantinos Papamichael
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Patent number: 10958717Abstract: A server system is provided that includes a plurality of servers, each server including at least one hardware acceleration device and at least one processor communicatively coupled to the hardware acceleration device by an internal data bus and executing a host server instance, the host server instances of the plurality of servers collectively providing a software plane, and the hardware acceleration devices of the plurality of servers collectively providing a hardware acceleration plane that implements a plurality of hardware accelerated services, wherein each hardware acceleration device maintains in memory a data structure that contains load data indicating a load of each of a plurality of target hardware acceleration devices, and wherein a requesting hardware acceleration device routes the request to a target hardware acceleration device that is indicated by the load data in the data structure to have a lower load than other of the target hardware acceleration devices.Type: GrantFiled: August 30, 2019Date of Patent: March 23, 2021Assignee: Microsoft Technology Licensing, LLCInventors: Adrian Michael Caulfield, Eric S. Chung, Michael Konstantinos Papamichael, Douglas C. Burger, Shlomi Alkalay
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Publication number: 20210044679Abstract: A masked packet checksum is utilized to provide error detection and/or error correction for only discrete portions of a packet, to the exclusion of other portions, thereby avoiding retransmission if transmission errors appear only in portions excluded by the masked packet checksum. A bitmask identifies packet portions whose data is to be protected with error detection and/or error correction schemes, packet portions whose data is to be excluded from such error detection and/or error correction schemes, or combinations thereof. A bitmask can be a per-packet specification, incorporated into one or more fields of individual packets, or a single bitmask can apply equally to multiple packets, which can be delineated in numerous ways, and can be separately transmitted or derived. Bitmasks can be generated at higher layers with lower layer mechanisms deactivated, or can be generated lower layers based upon data passed down.Type: ApplicationFiled: August 9, 2019Publication date: February 11, 2021Inventors: Adrian Michael CAULFIELD, Michael Konstantinos PAPAMICHAEL
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Patent number: 10812415Abstract: Active intelligent message filtering can be utilized to provide error resiliency, thereby allowing messages to be received without traditional error detection, and, in turn, avoiding the inefficiency of retransmission of network communications discarded due to network transmission errors detected by such traditional error detection mechanisms. Network transmission errors can result in the receiving application receiving messages that appear to comprise values that differ from the values originally transmitted by the transmitting application. Based on the inaccuracy tolerance applicable to the transmitting and receiving applications, rules can be applied to actively intelligently filter the received messages to replace the received values with the replacement values according to the rules. In such a manner, the receiving application can continue to receive usable data from the transmitting application without any error detection at lower network communication levels.Type: GrantFiled: August 13, 2019Date of Patent: October 20, 2020Assignee: Microsoft Technology Licensing, LLCInventors: Adrian Michael Caulfield, Michael Konstantinos Papamichael
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Publication number: 20200272579Abstract: Techniques are disclosed for implementing direct memory access in a virtualized computing environment. A new mapping of interfaces between RNIC Consumer and RDMA Transport is defined, which enables efficient retry, a zombie detection mechanism, and identification and handling of invalid requests without bringing down the RDMA connection. Techniques are disclosed for out of order placement and delivery of ULP Requests without constraining the RNIC Consumer to the ordered networking behavior, if it is not required for the ULP (e.g., storage). This allows efficient deployment of an RDMA accelerated storage workload in a lossy network configuration, and reduction in latency jitter.Type: ApplicationFiled: February 22, 2019Publication date: August 27, 2020Inventors: Matthew Graham HUMPHREY, Vadim MAKHERVAKS, Michael Konstantinos PAPAMICHAEL
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Publication number: 20200274832Abstract: Techniques are disclosed for implementing direct memory access in a virtualized computing environment. A new mapping of interfaces between RNIC Consumer and RDMA Transport is defined, which enables efficient retry, a zombie detection mechanism, and identification and handling of invalid requests without bringing down the RDMA connection. Techniques are disclosed for out of order placement and delivery of ULP Requests without constraining the RNIC Consumer to the ordered networking behavior, if it is not required for the ULP (e.g., storage). This allows efficient deployment of an RDMA accelerated storage workload in a lossy network configuration, and reduction in latency jitter.Type: ApplicationFiled: February 22, 2019Publication date: August 27, 2020Inventors: Matthew Graham HUMPHREY, Vadim MAKHERVAKS, Michael Konstantinos PAPAMICHAEL
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Publication number: 20190394260Abstract: A server system is provided that includes a plurality of servers, each server including at least one hardware acceleration device and at least one processor communicatively coupled to the hardware acceleration device by an internal data bus and executing a host server instance, the host server instances of the plurality of servers collectively providing a software plane, and the hardware acceleration devices of the plurality of servers collectively providing a hardware acceleration plane that implements a plurality of hardware accelerated services, wherein each hardware acceleration device maintains in memory a data structure that contains load data indicating a load of each of a plurality of target hardware acceleration devices, and wherein a requesting hardware acceleration device routes the request to a target hardware acceleration device that is indicated by the load data in the data structure to have a lower load than other of the target hardware acceleration devices.Type: ApplicationFiled: August 30, 2019Publication date: December 26, 2019Applicant: Microsoft Technology Licensing, LLCInventors: Adrian Michael Caulfield, Eric S. Chung, Michael Konstantinos Papamichael, Douglas C. Burger, Shlomi Alkalay
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Patent number: 10425472Abstract: A server system is provided that includes a plurality of servers, each server including at least one hardware acceleration device and at least one processor communicatively coupled to the hardware acceleration device by an internal data bus and executing a host server instance, the host server instances of the plurality of servers collectively providing a software plane, and the hardware acceleration devices of the plurality of servers collectively providing a hardware acceleration plane that implements a plurality of hardware accelerated services, wherein each hardware acceleration device maintains in memory a data structure that contains load data indicating a load of each of a plurality of target hardware acceleration devices, and wherein a requesting hardware acceleration device routes the request to a target hardware acceleration device that is indicated by the load data in the data structure to have a lower load than other of the target hardware acceleration devices.Type: GrantFiled: January 17, 2017Date of Patent: September 24, 2019Assignee: MICROSOFT TECHNOLOGY LICENSING, LLCInventors: Adrian Michael Caulfield, Eric S. Chung, Michael Konstantinos Papamichael, Douglas C. Burger, Shlomi Alkalay
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Publication number: 20190284871Abstract: The disclosed embodiments relate to the design of a system that controls a dynamic-shading system for a window/skylight. This system includes a photosensor array, and an optical element having a field of view corresponding to the window/skylight, which directs light onto the photosensor array. It also includes a processing mechanism that automatically generates a digital luminance map from signals received through the photosensor array to determine locations of one or more light sources in the field of view. The processing mechanism also automatically controls the dynamic-shading system in response to the determined locations of the one or more light sources.Type: ApplicationFiled: April 24, 2017Publication date: September 19, 2019Applicant: The Regents of the University of CaliforniaInventor: Konstantinos Papamichael
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Publication number: 20180205785Abstract: A server system is provided that includes a plurality of servers, each server including at least one hardware acceleration device and at least one processor communicatively coupled to the hardware acceleration device by an internal data bus and executing a host server instance, the host server instances of the plurality of servers collectively providing a software plane, and the hardware acceleration devices of the plurality of servers collectively providing a hardware acceleration plane that implements a plurality of hardware accelerated services, wherein each hardware acceleration device maintains in memory a data structure that contains load data indicating a load of each of a plurality of target hardware acceleration devices, and wherein a requesting hardware acceleration device routes the request to a target hardware acceleration device that is indicated by the load data in the data structure to have a lower load than other of the target hardware acceleration devices.Type: ApplicationFiled: January 17, 2017Publication date: July 19, 2018Applicant: Microsoft Technology Licensing, LLCInventors: Adrian Michael Caulfield, Eric S. Chung, Michael Konstantinos Papamichael, Douglas C. Burger, Shlomi Alkalay
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Publication number: 20160192459Abstract: The disclosed embodiments relate to a household appliance (such as a refrigerator, stove, microwave, toaster, oven, dishwasher, clothes washer and clothes dryer) that includes exterior and/or interior light sources that can adjust their spectral illumination based on an ambient light level. The household appliance may include a door that an individual may open to access the contents within the household appliance's interior. The household appliance also comprises a light sensor that is configured to detect the ambient light level outside the household appliance. The household appliance further comprises one or more internal light sources that are located within the household appliance's interior. The internal light sources are configured to emit a low-intensity light when the door is open and when the light sensor detects an ambient light level that falls below a threshold value.Type: ApplicationFiled: March 9, 2016Publication date: June 30, 2016Applicant: The Regents of the University of CaliforniaInventors: Michael Siminovitch, Konstantinos Papamichael, Keith Graeber
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Patent number: 8876335Abstract: A modular lighting system for lighting a work area is disclosed. The system includes a power supply with power outlets for powering LED fixtures. The power supply preferably operates at or below a fixed power output level, such as to illuminate the work area using less than 0.2 Watts per square foot of energy. The lighting system also includes an occupancy sensor and/or a light level sensor for controlling lighting levels in the work area in response to detection of a person, ambient light levels and/or a combination thereof. The lighting system can also include computer unit with a micro-processor and a memory unit for running software or firmware the executes lighting programs, stores light usage histories and/or provides system reports to a remote computer by a wireless means and/or over a computer network.Type: GrantFiled: April 30, 2014Date of Patent: November 4, 2014Assignees: Finelite Inc, The Regents of the University of CaliforniaInventors: Walter Blue Clark, Douglas Joseph Scott Bourne, Erik R. Page, Michael Siminovitch, Kevin Gauna, Konstantinos Papamichael
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Patent number: 8820959Abstract: A lighting fixture system, comprising a first illuminant, a secondary illuminant; and a sensor configured to detect a predetermined condition, the sensor being coupled to the first illuminant and the secondary illuminant, the first illuminant and the secondary illuminant comprising different light sources, the sensor configured to cause modulation of the first illuminant and the secondary illuminant in response to detection of the pre-determined condition.Type: GrantFiled: January 3, 2012Date of Patent: September 2, 2014Inventors: Michael O. Nevins, Keith E. Graeber, Michael Jay Siminovitch, Konstantinos Papamichael
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Publication number: 20140232267Abstract: A modular lighting system for lighting a work area is disclosed. The system includes a power supply with power outlets for powering LED fixtures. The power supply preferably operates at or below a fixed power output level, such as to illuminate the work area using less than 0.2 Watts per square foot of energy. The lighting system also includes an occupancy sensor and/or a light level sensor for controlling lighting levels in the work area in response to detection of a person, ambient light levels and/or a combination thereof. The lighting system can also include computer unit with a micro-processor and a memory unit for running software or firmware the executes lighting programs, stores light usage histories and/or provides system reports to a remote computer by a wireless means and/or over a computer network.Type: ApplicationFiled: April 30, 2014Publication date: August 21, 2014Applicants: Finelite INC., University of California, David, The Regents of the University of CaliforniaInventors: Walter Blue Clark, Douglas Joseph Scott Bourne, Erik R. Page, Michael Siminovitch, Kevin Gauna, Konstantinos Papamichael
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Patent number: 8632209Abstract: A lighting fixture system, comprising a first illuminant, a secondary illuminant; and a sensor configured to detect a predetermined condition, the sensor being coupled to the first illuminant and the secondary illuminant, the first illuminant and the secondary illuminant comprising different light sources, the sensor configured to cause modulation of the first illuminant and the secondary illuminant in response to detection of the pre-determined condition.Type: GrantFiled: July 28, 2011Date of Patent: January 21, 2014Assignees: Full Spectrum Solutions, The Regents of the University of CaliforniaInventors: Keith E. Graeber, Michael Olen Nevins, Michael Jay Siminovitch, Konstantinos Papamichael
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Patent number: 8373547Abstract: One embodiment of the present invention provides a system that uses power-line phase-cut signaling to change energy usage for one or more devices that share a common power signal. During operation, the system receives a request to change power usage. In response to the request, the system inserts a phase-cut notch into the common power signal. A device that is located downstream from the inserted phase-cut notch detects this notch in the common power signal, and in response triggers a power-state change. For instance, the device may trigger a reduced-power state when it detects a phase-cut notch.Type: GrantFiled: May 24, 2007Date of Patent: February 12, 2013Assignees: Nev Electronics LLC, The Regents of the University of California, Benya Lighting DesignInventors: James R. Benya, Joel W. Snook, Erik R. Page, Michael Siminovitch, Konstantinos Papamichael, Margaret Aumann