Abstract: Certain aspects are directed to apparatus and techniques for estimating parasitic information associated with routing of a design using a pre-route version of the design. One example method generally includes determining one or more output features using a machine learning model based on a pre-route version of a design of an integrated circuit, where the one or more output features include a density map providing an estimate of a density of elements associated with a routed version of the design. The method also includes estimating parasitic information associated with the design based on the one or more output features, and outputting the parasitic information.

Abstract: Parasitic extraction is a useful tool for analyzing and improving timing and other characteristics of semiconductor chips. Parasitic resistance and capacitance values are determined and stored in arrays. The parasitic values are extracted for multiple corners with a single analysis of the layout. Multi-corner analysis is performed using the parasitic values thereby optimizing the timing across various temperature and process operating points.