Abstract: A device is provided, including a dielectric layer, a plurality of first conductive segments within the dielectric layer and spaced apart from each other by respective first spacings, and a plurality of second conductive segments within the dielectric layer and spaced apart from each other by respective second spacings. The plurality of second conductive segments may be over and spaced apart from the plurality of first conductive segments by the dielectric layer. A respective one of the first conductive segments may at least partially extend across a corresponding one of the second spacings, and a respective one of the second conductive segments may at least partially extend across a corresponding one of the first spacings.

Abstract: The present disclosure generally relates to an electronic assembly. The electronic assembly may include a substrate including a plurality of first contact pads, a plurality of second contact pads, and a plurality of third contact pads. The electronic assembly may include a first device including a first footprint coupled to the substrate at a first surface. The electronic assembly may include a frame arranged between the first device and the substrate, the frame including a dielectric material, the frame further including a main frame extending around the first device, and further including a plurality of sub-frames encircling the plurality of first contact pads and the plurality of second contact pads on the substrate, wherein the frame may further include a conductive layer extending at least partially across the main frame.

Abstract: A device is provided, including a package substrate including at least one opening extending through the package substrate, and an interconnect structure including a first segment and a second segment. The first segment may extend under a bottom surface of the package substrate and may further extend beyond a footprint of the package substrate. The second segment may extend vertically from the first segment and may extend at least partially through the at least one opening of the package substrate.

Abstract: The present disclosure is directed to an electronic assembly and method of forming thereof. The electronic assembly may include a substrate and a first die with first and second opposing surfaces. The first die may be coupled to the substrate at the first surface. At least one first trench may extend partially through the first die from the second surface. A stiffener may be attached to the substrate. The stiffener may have a cavity that accommodates the first die, in which the second surface of the first die faces the stiffener. A thermally conductive layer may be positioned between the stiffener and the first die. The conductive layer at least partially fills the at least one first trench.

Abstract: A semiconductor package substrate includes an encapsulated interconnect on a land side of the substrate. The encapsulated interconnect includes an integral metallic structure that has a smaller contact end against the semiconductor package substrate, and a larger contact end for board mounting.

Abstract: A semiconductor package includes a package substrate, a base die including a first die surface coupled to the package substrate, and a second die surface opposite to the first die surface, and a first device including a first device surface coupled to the package substrate, and a second device surface opposite to the first device surface. The semiconductor package further includes a second device including a third device surface coupled to the second device surface, and a fourth device surface opposite to the third device surface, and a bridge including a first portion coupled to the package substrate, and a second portion coupled to the first portion, the fourth device surface and the second die surface.

Abstract: The present disclosure is directed to a printed circuit board having a composite upper surface with a first section of a first-type of printed circuit board and a second section of a second-type of printed circuit board, for which the first section of the first-type of printed circuit board and the second section of the second-type of printed circuit board are coupled, respectively, to at least one device that is configured to abridge the first and second sections of the composite upper surface. In an aspect, the second-type of printed circuit board is configured to be embedded in the first-type of printed circuit board and the first-type of printed circuit board is configured to receive the second-type of printed circuit board.

Abstract: A semiconductor package includes a silicon die including a first die surface coupled to a package substrate, a second die surface opposite to the first die surface, and at least one die sidewall orthogonal to the first die surface and the second die surface, and a mold layer including a first mold surface, a second mold surface opposite to the first mold surface, and at least one mold sidewall orthogonal to the first mold surface and the second mold surface, the at least one mold sidewall being disposed along the at least one die sidewall, and the mold layer further including a power conductive corridor extending from the first mold surface and coupled to the package substrate through the first mold surface. The semiconductor package further includes a first stacked device coupled to the first die surface and to the power conductive corridor through the first mold surface.

Abstract: A semiconductor package including: a package substrate including a base die disposed on a top surface of the package substrate, the base die including a plurality of electrical components disposed on a top surface of the base die, the plurality of electrical components including a first electrical component configured adjacent to a second electrical component, wherein the first electrical component and the second electrical component have an asymmetric form-factor; and a stiffener including: a stiffener main portion, wherein the stiffener main portion is affixed to the top surface of the package substrate and configured at least partially surrounding the base die; and a stiffener extension portion configured to extend from the stiffener main portion to be disposed at least partially over the top surface of the base die adjacent to the first electrical component and the second electrical component.

Abstract: An electronic circuit including a substrate having a first dielectric characteristic. The substrate can include a first side and a second side. An intermediary material can be disposed within the substrate. For instance, the intermediary material can be located between the first side and the second side. The intermediary material can include a second dielectric characteristic, where the second dielectric characteristic is different than the first dielectric characteristic. A first conductive layer can be disposed on the first side, and a second conductive layer can be disposed on the second side. A conductive path can be electrically coupled between the first conductive layer and the second conductive layer. The conductive path can be in contact with at least a portion of the intermediary material.

Abstract: The technique described herein includes a device to address the electrical performance (e.g. signal integrity) degradation ascribed to electromagnetic interference and/or crosstalk coupling occur at tightly coupled (e.g. about 110 ?m pitch or less) interconnects, including the first level (e.g. the interconnection between a die and a package substrate). In some embodiments, this invention provides a conductive layer with a plurality of cavities to isolate electromagnetic coupling and/or interference between adjacent interconnects for electronic device performance scaling. In some embodiments, at least one interconnect joint is coupled to the conductive layer, and at least one interconnect joint is isolated from the conductive layer by a dielectric lining at least one of the cavities, the conductive layer being associated to a ground reference voltage by the interconnect joint coupled to the conductive layer.

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed to improve data training of a machine learning model using a field-programmable gate array (FPGA). An example system includes one or more computation modules, each of the one or more computation modules associated with a corresponding user, the one or more computation modules training first neural networks using data associated with the corresponding users, and FPGA to obtain a first set of parameters from each of the one or more computation modules, the first set of parameters associated with the first neural networks, configure a second neural network based on the first set of parameters, execute the second neural network to generate a second set of parameters, and transmit the second set of parameters to the first neural networks to update the first neural networks.

Abstract: The present disclosure generally relates to an electronic assembly. The electronic assembly may include a first substrate including a first surface, an opposing second surface and a recess opening extending through the first surface. The electronic assembly may also include a power delivery mold frame including a first mold surface, an opposing second mold surface, a plurality of first metal planes and a plurality of second metal planes extending between the first and second mold surfaces, the power delivery mold frame arranged in the recess opening and coupled to the first substrate through the first mold surface. The electronic assembly may further include a second substrate including a subsequent first surface, an opposing subsequent second surface, the second substrate coupled to the power delivery mold frame through a plurality of first solder bumps and further coupled to the first substrate through a plurality of second solder bumps at the subsequent first surface.

Abstract: Two conductive reference layers are embedded in a semiconductor package substrate. The embedded reference layers facilitate low electromagnetic noise coupling between adjacent signals for semiconductor device package.

Abstract: Foldable Compression Attached Memory Modules (fCAMMs) and associated apparatus, assemblies and systems. The fCAMM comprises a compression contact module having a plurality of contact means arranged in one or more arrays on its underside, first and second fold modules including multiple memory devices, and flexible interconnects coupling the compression contact module to the first and second fold modules. Under one assembled configuration, portions of printed circuit boards (PCBs) for the first and second fold modules are folded over portions of the compression contact module. Under another configuration, the first fold module is disposed above the second fold module, which is disposed above the compression contact module. In an assembly or system including a motherboard, a compression mount technology (CMT) connector or a land grid array (LGA) assembly is disposed between the motherboard and the compression contact module. Bolster plates are used to urge the compression contact module toward the motherboard.

Abstract: The present disclosure generally relates to a printed circuit board assembly that may include a circuit board having a first surface and an opposing second surface. The printed circuit board assembly may also include a first interconnect barrel disposed in the circuit board. The first interconnect barrel may have a first length extending between the first surface and the second surface. The first interconnect barrel may include a first section, and may further include a second section spaced apart from the first section by a first gap having a first depth extending partially through the first length. The printed circuit board assembly may further include a first conductive trace coupled to the first section and a second conductive trace coupled to the second section at a first terminal.

Abstract: The present disclosure is directed to multichip semiconductor packages, and methods for making them, which includes a package substrate with an integrated bridge frame having a first horizontal portion positioned on a top surface of the package substrate, with first and second dies positioned overlapping the first horizontal portion of the bridge frame, and a second horizontal portion positioned on the bottom surface of the package substrate, with third and fourth dies positioned overlapping the second horizontal portion of the bridge frame. The bridge frame further includes first and second vertical portions separated by a portion of the package substrate positioned under the first horizontal portion of the bridge frame between the top surface and bottom surfaces of the package substrate, and a plurality of vertical interconnects adjacent to the first and second vertical portions of the bridge frame.

Abstract: Apparatuses and methods for evaluating the risk factors of a proposed vehicle maneuver using remote data are disclosed. In embodiments, a computer-assisted/autonomous driving vehicle communicates with one or more remote data sources to obtain remote sensor data, and process such remote sensor data to determine the risk of a proposed vehicle maneuver. A remote data source may be authenticated and validated, such as by correlation with other remote data sources and/or local sensor data. Correlation may include performing object recognition upon the remote data sources and local sensor data. Risk evaluation is performed on the validated data, and the results of the risk evaluation presented to a vehicle operator or to an autonomous vehicle navigation system.

Abstract: Methods, apparatus, systems, and articles of manufacture for allocating a workload to an accelerator using machine learning are disclosed. An example apparatus includes a workload attribute determiner to identify a first attribute of a first workload and a second attribute of a second workload. An accelerator selection processor causes at least a portion of the first workload to be executed by at least two accelerators, accesses respective performance metrics corresponding to execution of the first workload by the at least two accelerators, and selects a first accelerator of the at least two accelerators based on the performance metrics. A neural network trainer trains a machine learning model based on an association between the first accelerator and the first attribute of the first workload. A neural network processor processes, using the machine learning model, the second attribute to select one of the at least two accelerators to execute the second workload.

Abstract: The present disclosure relates to a semiconductor package that may include a substrate. The substrate may have a top surface and a bottom surface. The semiconductor package may include an opening in the substrate. The semiconductor package may include a bridge disposed in the opening. The bridge may have an upper end at the top surface of the substrate and a lower end at the bottom surface of the substrate. The semiconductor package may include a first die on the top surface of the substrate at least partially extending over a first portion of the upper end of the bridge. The semiconductor package may include a second die on the bottom surface of the substrate at least partially extending over the lower end of the bridge. The bridge may couple the first die to the second die.