Abstract: Provided is a memory switching control apparatus using an open serial interfacing scheme capable of enhancing flexibility, reliability, availability, performance in a data communication processes between a memory and a processing unit and an operating method thereof. The memory switching control apparatus includes: one or more processor interfacing units which perform interfacing with one or more processing units; one or more memory interfacing units which have open-serial-interfacing-scheme memory interfacing ports to interface with data storage devices connected to the memory interfacing ports in a serial interfacing scheme; and a plurality of arbitrating units which are provided corresponding to the memory interfacing units to independently arbitrate usage rights of the processor interfacing units to the memory interfacing units.

Abstract: An apparatus for processing packets in a high speed router and a method thereof are provided. The high speed router includes a forward processor and a control processor where the forward processor having an input terminal processor and an output terminal processor. The output terminal processor manages a Layer 2 Address Table by dividing the Layer 2 Address Table into a layer 2 indirect address table and a layer 2 direct address table and by managing them. The indirect address table is directly indexed in the Next-hop Table of the input terminal processor table. The direct address table is composed of a hashing table for a destination IP address. Therefore, the system efficiency can be improved by reducing the memory which is used for storing the forwarding information table occupied by the forward processor and by reducing the IPC message between the control processor and the forwarding process.

Abstract: Provided is a memory switching control apparatus using an open serial interfacing scheme capable of enhancing flexibility, reliability, availability, performance in a data communication processes between a memory and a processing unit and an operating method thereof. The memory switching control apparatus includes: one or more processor interfacing units which perform interfacing with one or more processing units; one or more memory interfacing units which have open-serial-interfacing-scheme memory interfacing ports to interface with data storage devices connected to the memory interfacing ports in a serial interfacing scheme; and a plurality of arbitrating units which are provided corresponding to the memory interfacing units to independently arbitrate usage rights of the processor interfacing units to the memory interfacing units.