Patents by Inventor Kook-Jui Tai

Kook-Jui Tai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7666779
    Abstract: A semiconductor device and a fabrication method thereof are provided. A semiconductor substrate having a plurality of bonding pads is prepared, and a first passivation layer, a second passivation layer and a metallic layer are successively formed on the semiconductor substrate. A third passivation layer is further applied on the semiconductor substrate and has a plurality of openings for exposing a portion of the metallic layer, wherein each of the openings is shifted in position from a corresponding one of the bonding pads by a distance not exceeding a radius of the bonding pad. A plurality of solder bumps are bonded to the exposed portion of the metallic layer and have a larger contact area with the third passivation layer. This provides better buffer to reduce stress exerted on the solder bumps, thereby preventing problems of cracking and delamination as in the prior art.
    Type: Grant
    Filed: April 1, 2008
    Date of Patent: February 23, 2010
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Chun-Chi Ke, Kook-Jui Tai, Chien-Ping Huang
  • Publication number: 20080182401
    Abstract: A semiconductor device and a fabrication method thereof are provided. A semiconductor substrate having a plurality of bonding pads is prepared, and a first passivation layer, a second passivation layer and a metallic layer are successively formed on the semiconductor substrate. A third passivation layer is further applied on the semiconductor substrate and has a plurality of openings for exposing a portion of the metallic layer, wherein each of the openings is shifted in position from a corresponding one of the bonding pads by a distance not exceeding a radius of the bonding pad. A plurality of solder bumps are bonded to the exposed portion of the metallic layer and have a larger contact area with the third passivation layer. This provides better buffer to reduce stress exerted on the solder bumps, thereby preventing problems of cracking and delamination as in the prior art.
    Type: Application
    Filed: April 1, 2008
    Publication date: July 31, 2008
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Chun-Chi Ke, Kook-Jui Tai, Chien-Ping Huang
  • Patent number: 7355279
    Abstract: A semiconductor device and a fabrication method thereof are provided. A semiconductor substrate having a plurality of bonding pads is prepared, and a first passivation layer, a second passivation layer and a metallic layer are successively formed on the semiconductor substrate. A third passivation layer is further applied on the semiconductor substrate and has a plurality of openings for exposing a portion of the metallic layer, wherein each of the openings is shifted in position from a corresponding one of the bonding pads by a distance not exceeding a radius of the bonding pad. A plurality of solder bumps are bonded to the exposed portion of the metallic layer and have a larger contact area with the third passivation layer. This provides better buffer to reduce stress exerted on the solder bumps, thereby preventing problems of cracking and delamination as in the prior art.
    Type: Grant
    Filed: September 13, 2005
    Date of Patent: April 8, 2008
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Chun-Chi Ke, Kook-Jui Tai, Chien-Ping Huang
  • Publication number: 20070075423
    Abstract: A semiconductor element with conductive bumps and a fabrication method thereof are provided. The fabrication method includes providing a semiconductor element having a plurality of bond pads formed on an active surface thereof, wherein each of the bond pads has a predetermined bonding area; applying a passivation layer on the active surface, with a plurality of openings formed for exposing the predetermined bonding areas; applying a buffer layer on the passivation layer to cover the predetermined bonding areas; allowing the buffer layer with a plurality of openings to be formed for exposing a portion of the predetermined bonding areas; forming a under bump metallurgy (UBM) layer on the bond pads, allowing the predetermined bonding areas to be completely covered by the UBM layer; and implanting conductive bumps on the UBM layer. The buffer layer advantageously absorbs stresses exerted to the conductive bumps, thereby preventing the conducting bumps from cracking.
    Type: Application
    Filed: December 6, 2005
    Publication date: April 5, 2007
    Applicant: Siliconware Precision Industries Co., Ltd.
    Inventors: Chun-Chi Ke, Kook-Jui Tai, Chien-Ping Huang
  • Publication number: 20070023925
    Abstract: A semiconductor device and a fabrication method thereof are provided. A first passivation layer and a second passivation layer are applied on a semiconductor substrate having at least one bond pad, with the bond pad being exposed. A first metallic layer is formed on the second passivation layer and electrically connected to the bond pad. A third passivation layer is applied on the first metallic layer and exposes a portion of the first metallic layer. A second metallic layer is formed on the third passivation layer and electrically connected to the exposed portion of the first metallic layer. A fourth passivation layer is applied on the second metallic layer and has an opening corresponding in position to the bond pad, allowing a portion of the second metallic layer to be exposed via the opening, such that a solder bump is formed on the exposed portion of the second metallic layer.
    Type: Application
    Filed: April 27, 2006
    Publication date: February 1, 2007
    Applicant: Siliconware Precision Industries Co., Ltd.
    Inventors: Chun-Chi Ke, Kook-Jui Tai, Chien-Ping Huang
  • Publication number: 20060258137
    Abstract: A semiconductor device and a fabrication method thereof ate provided. A semiconductor substrate having a plurality of bonding pads is prepared, and a first passivation layer, a second passivation layer and a metallic layer are successively formed on the semiconductor substrate. A third passivation layer is further applied on the semiconductor substrate and has a plurality of openings for exposing a portion of the metallic layer, wherein each of the openings is shifted in position from a corresponding one of the bonding pads by a distance not exceeding a radius of the bonding pad. A plurality of solder bumps are bonded to the exposed portion of the metallic layer and have a larger contact area with the third passivation layer. This provides better buffer to reduce stress exerted on the solder bumps, thereby preventing problems of cracking and delamination as in the prior art.
    Type: Application
    Filed: September 13, 2005
    Publication date: November 16, 2006
    Applicant: Siliconware Precision Industries Co., Ltd.
    Inventors: Chun-Chi Ke, Kook-Jui Tai, Chien-Ping Huang