Abstract: Data bits are prefetched from memory cells in parallel and are read out serially. The memory includes multiple stages (1710) of latches through which the parallel data is transferred before being read out serially. The multiple stages provide suitable delays to satisfy variable latency requirements (e.g. CAS latency in DDR2). The first bit for the serial output bypasses the last stage (1710.M). In some embodiments, the control signals controlling the stages other than the last stage in their providing the first data bit to the memory output are not functions of the control signals controlling the last stage providing the subsequent data bits to the memory output.

Abstract: Data bits are prefetched from memory cells in parallel and are read out serially. The memory includes multiple stages (1710) of latches through which the parallel data is transferred before being read out serially. The multiple stages provide suitable delays to satisfy variable latency requirements (e.g. CAS latency in DDR2). The first bit for the serial output bypasses the last stage (1710.M). In some embodiments, the control signals controlling the stages other than the last stage in their providing the first data bit to the memory output are not functions of the control signals controlling the last stage providing the subsequent data bits to the memory output.

Abstract: In order to reduce a cycle time and enable a high-speed operation in a semiconductor memory, the memory is constructed having a multi-pipeline structure. The multi-pipeline structure, for instance, includes a three-stage pipeline, in which an additional data register is introduced between a sense amplifier and a main data line. The remaining memory structure can be configured in a manner comparable to that of a conventional two-stage pipeline semiconductor memory.

Abstract: In order to reduce a cycle time and enable a high-speed operation in a semiconductor memory, the memory is constructed having a multi-pipeline structure. The multi-pipeline structure, for instance, includes a three-stage pipeline, in which an additional data register is introduced between a sense amplifier and a main data line. The remaining memory structure can be configured in a manner comparable to that of a conventional two-stage pipeline semiconductor memory.

Abstract: An electrostatic discharge (ESD) protection transistor for discharging current from an ESD event present on an input/output pad. The ESD protection transistor is capable of improved discharging of excessive current without damage to the semiconductor device and to the ESD protection transistor itself. The ESD protection transistor includes a first conductive line connecting an input/output pad to the source and drain of the transistor at multiple points preventing the convergence of an excessive current at a certain point and ESD damage to the transistor. The transistor also includes a second conductive line formed on an insulating layer such that it does not overlap with the first conductive line.

Abstract: A clock monitor circuit includes a first and second delay and clock signal generating unit for receiving a clock signal and an inverted clock signal, respectively. The first and second delay and clock signal generating units generate a first and second signals, respectively. A logic sum unit logically-sums the first and second signals to generate a stop clock signal. The clock monitor circuit according to the present invention can monitor the presence of a clock signal irrespective of an operation cycle of the clock signal. Further, the synchronous semiconductor memory device utilizing the clock monitor circuit according to the present invention is adapted to consume electric current only when a clock signal is present. That is, the device does not consume electric current when the clock signal is not present thereby reducing unnecessary waste of electric power in the stand-by mode.

Abstract: An internal clock generating circuit of a synchronous type semiconductor memory device includes a transmission part for transmitting a first clock enable signal in response to applying a first level of a first clock signal. It also includes a latch part for latching the first clock enable signal transmitted from the transmission part. A gating part gates the latched first clock enable signal with the first clock signal to generate a second clock signal as an internal clock signal for the memory device. This reduces a time lag by which the speed of the internal clock is synchronized with the external clock signal.

Abstract: Disclosed is a high speed semiconductor memory device, which includes a memory cell to which a pair of bit lines are coupled and a discharge circuit for sufficiently discharging one of the bit lines which is being pulled down to a low voltage level in a write operation. Thus, in spite of a short write cycle time, the write operation speed of the memory can be improved without the imperfection in writing a data into the memory cell.

Abstract: A method for precharging a bit line pair or data line pair in a semiconductor memory device includes generating a precharge pulse signal when a write enable line is deactivated at the beginning of a read cycle. The line pair is rapidly precharged by a pair of large transistors which turn on in response to the pulse signal. The pulse signal ends and turns of the transistors before a word line is enabled during the read cycle to prevent the large transistors from interfering with the bit sensing operation. A precharge circuit for precharging a bit line pair or data line pair in a semiconductor memory device includes a pulse generator having a delay circuit that determines the pulse width of a precharge pulse which is generated when a write enable line is deactivated. A write and precharge circuit includes two large transistors connected between a line pair and a power source that turn on and rapidly precharge the line pair during the precharge pulse.

Abstract: A high-speed data output related circuit for a memory device reduces the operational cycle time by self-latching data in a data output buffer and self-resetting a main sense amplifier and level shifter, thereby the need for external control signals.

Abstract: Methods and apparatus are disclosed for receiving and decoding address information applied to a synchronous semiconductor memory device. Separate read address and write address decoders and latches are provided for decoding the address without waiting for a determination as to whether a read cycle or a write cycle is undertaken, thereby reducing the decoding delay and thereby increasing the speed of such a device in operation.

Abstract: A data output buffer circuit for a semiconductor memory device operates with two separate power supplies and prevents malfunctions caused by the sequence in which the power supplies are energized. At lease one discharge transistor is used to remove charge from the gate of one or more NMOS push-pull transistors in an output buffer which can be floating in a charged state if one of the power supplies is energized before the other. In one embodiment, the gates of two discharge transistors are cross-coupled to the gates of the push-pull transistors to assure that at least one of the push-pull transistors are turned off. In an alternative embodiment, one or more discharge transistors are connected to the gates of at least one push-pull transistor and are controlled by a pulse generator that generates a pulse signal in response to variations in the voltage of the power supply for the push-pull transistors.

Abstract: A burn-in test circuit for a semiconductor memory device tests for defective memory cells. The test circuit applies a test signal that turns "off" transistors in a precharge circuit and applies a select signal to memory cells at predetermined intervals. The select signal and test signal are delayed for different time intervals depending on whether the memory device is transitioning from a normal operating mode to a test mode or from the test mode to the normal operating mode. The selective delay prevents overcurrent conditions from occurring during the mode transitions.

Abstract: Integrated circuit chips with fuse-based mode selection capability include a first signal generator for storing a first logic state when the fuse is blown, in response to an externally generated input signal, and for generating a first option changing signal based on the stored first logic state. To reduce the susceptibility to noise and inadvertent designation signals, a second signal generator for storing a second logic state when the fuse is blown is also provided and that fuse is blown in response another externally generated input signal. However, rather than blowing the fuses of the first option changing signal generator and the second option changing signal generator by applying external input signals simultaneously, the fuses are blown sequentially by connecting the second option changing signal generator in series with the first option changing signal generator so that the second option changing signal cannot be generated unless the first option changing signal generator has already been generated.