Abstract: An apparatus and a system for viewing a 3D image including a synchronization signal receiver for receiving 3D image synchronization signal; a 3D control signal generator for generating left-eye glass control signal and a right-eye glass control signal in accordance with the synchronization signal received; a left-eye glass that opens or intercepts light transmitted to the left-eye glass; a right-eye glass that opens or intercepts light transmitted to the right-eye glass; a central processor that controls operation of the 3D control signal generator and transmits the synchronization signal to the 3D control signal generator; and a power controller that connects or intercepts power supplied to the synchronization signal receiver and the central processor. The power consumption of the apparatus is minimized by supplying power to the synchronization signal receiver and the central processor at a time when the synchronization signal is received and power is intercepted during the rest period.

Abstract: Disclosed herein is a pad controlling apparatus controlling current and voltage applied to a pad, the pad controlling apparatus including: a voltage drop unit dropping the voltage applied to the pad; a switching unit connected in parallel with the voltage drop unit; and a control unit comparing a level of the dropped voltage and first reference voltage with each other and turning on the switching unit on when the level of the dropped voltage is larger than the first reference voltage. According to the present invention, even though interrupt occurs from the outside, a chip may be normally operated.

Abstract: Disclosed herein is a multi-voltage regulator. The multi-voltage regulator includes an error amplifier amplifying a difference voltage between a predetermined reference voltage and a received feedback voltage; a first voltage adjusting part connected to an output terminal of the error amplifier, the first voltage adjusting part regulating a level of a voltage at a power input terminal to output the regulated voltage to a first output terminal; a second voltage adjusting part connected to the output terminal of the error amplifier, the second voltage adjusting part regulating the level of the voltage at the power input terminal to output the regulated voltage to a second output terminal; and a voltage detector detecting a voltage according to a voltage at the first output terminal and a voltage at the second output terminal to supply the detected voltage as the feedback voltage.

Abstract: There are provided a wireless personal area networks (WPAN) Zigbee receiver and a receiving method thereof that can obtain a spreading gain by a reduction in data rate. A wireless personal area network Zigbee receiver receiving a signal packet including a plurality of functional units having a plurality of symbols, the plurality of functional units each repeated as many as a predetermined extension number according to an aspect of the invention includes: a preamble detection unit detecting a, and generating a preamble synchronization; and an SFD synchronization unit comparing, each symbol of SFD units included in the signal packet with a predetermined SFD reference symbol continuously and repeatedly as many as the extension number, and generating an SFD synchronization signal when each of the symbols of the SFD units is equal to the SFD reference symbol as many as the extension number.

Abstract: Provided is a low-power ZigBee device provided with a sleeping mode and an active mode including a power supplying unit for supplying a power; a Medium Access Control (MAC) processing unit for receiving a wake-up packet and for controlling a modem unit and an Radio Frequency (RF) unit; and a Central Processing Unit (CPU) for receiving and processing a data packet, wherein the MAC processing unit makes the power supplying unit apply a power to the CPU based on a result of checking an identification (ID) of the wake-up packet.

Abstract: Disclosed herein are a 3D TV and a system using RF wireless communication and a method for synchronizing a 3D TV system using the same. In the 3D TV system using the RF wireless communication according to an exemplary embodiment of the present invention, two or more 3D TVs transmit and receive synchronous signals through the RF wireless communication, thereby locking the screen synchronization and synchronous signals of the 3D TVs. Thereafter, when the 3D TVs transmits the synchronous signals to the 3D spectacles, the synchronous signals including the time offset are transmitted, having different time difference. As a result, the 3D spectacles can be synchronized with images displayed on the 3D TVs by using time offset information.

Abstract: The present invention provides a digital amplitude modulator and polar transmitter using the same. The polar transmitter includes: a polar converter for converting an input signal into an amplitude information signal and a phase information signal, and outputting the converted amplitude and phase information signal; a sigma-delta modulator for receiving a fractional part of the amplitude information signal, and generating a correcting value for an integer part of the amplitude information signal; a phase-modulator for upward-modulating the phase information signal outputted from the polar converter, and outputting carrier waves including the upward-modulated phase information signal; and a digital power amplifier for generating an output signal whose amplitude corresponds to the integer part of the amplitude information signal which is subjected to correction by the correcting value, and outputting combining the output signal with an output value of the phase-modulator to output the combined signal.

Abstract: An apparatus and a system for viewing a 3D image including a synchronization signal receiver for receiving 3D image synchronization signal; a 3D control signal generator for generating left-eye glass control signal and a right-eye glass control signal in accordance with the synchronization signal received; a left-eye glass that opens or intercepts light transmitted to the left-eye glass; a right-eye glass that opens or intercepts light transmitted to the right-eye glass; a central processor that controls operation of the 3D control signal generator and transmits the synchronization signal to the 3D control signal generator; and a power controller that connects or intercepts power supplied to the synchronization signal receiver and the central processor. The power consumption of the apparatus is minimized by supplying power to the synchronization signal receiver and the central processor at a time when the synchronization signal is received and power is intercepted during the rest period.

Abstract: A direct sequence spread spectrum (DSSS) transceiver including a DSSS transmitter and a DSSS receiver, wherein the DSSS transmitter includes: an integral code mapping unit mapping source bit data in one of 2N (N is a natural number) of predetermined symbols by N bits and mapping the symbol in one of integral code words that are obtained by previously integrating each of 2N of bi-orthogonal code words; and a radio frequency (RF) transmitting unit transmitting the integral code words mapped by the integral code mapping unit over an RF carrier wave, and the DSSS receiver includes: an RF receiving unit removing an RF carrier wave from an RF signal from the RF transmitting unit and converting an analog signal obtained by removing the RF carrier wave from the RF signal into a digital signal; a differential circuit unit differentiating and converting the digital signal from the RF receiving unit into bi-orthogonal code words; and a symbol detection unit detecting a symbol corresponding to a maximum value of correlat

Abstract: Provided is an apparatus for controlling lighting brightness including a light control unit that generates a control signal for controlling the brightness of a plurality of lightings; a digital signal generating unit that converts a signal corresponding to the control signal at each period so as to generate non-periodic digital signals; and a driving voltage generating unit that generate driving voltages by converting the digital signals into analog signals.

Abstract: A timing estimator of an OQPSK demodulator is provided. In the timing estimator, an A/D converter converts an analog reception signal into a digital reception signal. A differential circuit section delays the digital reception signal from the A/D converter by a preset time and obtains a phase difference between a conjugate complex number signal of the delayed digital reception signal and the digital reception signal to offset a frequency error contained in the digital reception signal. A correlation operation section performs a correlation operation between a reference symbol differentiated in the same way as a differentiation of the differential circuit section and the reception signal to obtain each correlation value. A coherent detector detects a coherent point on the basis of the correlation value from the correlation operation section.

Abstract: Provided is a low-power ZigBee device provided with a sleeping mode and an active mode including a power supplying unit for supplying a power; a Medium Access Control (MAC) processing unit for receiving a wake-up packet and for controlling a modem unit and an Radio Frequency (RF) unit; and a Central Processing Unit (CPU) for receiving and processing a data packet, wherein the MAC processing unit makes the power supplying unit apply a power to the CPU based on a result of checking an identification (ID) of the wake-up packet.

Abstract: Provided is a data communication system including a first-in first-out (FIFO) buffer having a fixed size; a central processing unit (CPU) that writes data stored in a memory into the FIFO buffer; a modem that reads the data written by the CPU from the FIFO buffer; and a modem controller that is connected to the FIFO buffer, the CPU, and the modem, respectively, and controls the CPU such that data having a larger volume than the size of the FIFO buffer can be processed.

Abstract: The present invention relates to a multiple differential demodulator using a weighting value. The multiple differential demodulator according to the present invention includes a weighting value generator for integrating a real part and an imaginary part of a value acquired by multiplying one of a plurality of differentiated reception signals by a conjugated value of a differentiated PN code signal corresponding to a preset symbol, and determining the greater of the integrated real and integrated imaginary parts to apply a predetermined weighting value to the greater value, where the PN code signal is differentiated in the same fashion as the differentiated reception signals.

Abstract: An RC oscillation circuit and method capable of adjusting an oscillation frequency includes: an RC oscillator including a variable resistor and a variable capacitor, the RC oscillator generating an RC oscillating signal having a frequency determined by a resistance of the variable resistor and a capacitance of the variable capacitor; a counter counting a clock number of a reference oscillating signal corresponding to one period of the RC oscillating signal to generate a first count value, the reference oscillating signal having a preset frequency; and a frequency controller controlling a frequency of the RC oscillating signal by determining the resistance of the variable resistor and the capacitance of the variable capacitor such that a difference between the first count value and a preset second count value is smaller than a preset first critical value.

Abstract: The invention relates to a symbol detector for detecting symbols received in a receive modem of short-range wireless personal area network of a ZigBee system (IEEE 802.15.4). An OQPSK short-range wireless communication system according to the invention acquires frequency offset in a received signal using a symbol contained in a preamble of a packet of the signal, multi-delay-differentiates the signal by a plurality of predetermined delay times, and complex-conjugates the acquired frequency offset to eliminate the frequency offset. Then, the OQPSK short-range wireless communication system according to the invention correlates the received signal with a PN sequence delay-differentiated through the same process to detect the symbols corresponding to the received signal.

Abstract: Provided is an apparatus for controlling lighting brightness including a light control unit that generates a control signal for controlling the brightness of a plurality of lightings; a digital signal generating unit that converts a signal corresponding to the control signal at each period so as to generate non-periodic digital signals; and a driving voltage generating unit that generate driving voltages by converting the digital signals into analog signals.

Abstract: There is provided a lighting control apparatus using digital sigma-delta modulation, the apparatus including: a control part supplying a brightness control signal; a sigma-delta modulation part generating a carry signal according to the brightness control signal of the control part and a predetermined threshold signal by using a sigma-delta modulation method; and a lighting driving part generating a driving current according to the carry signal of the sigma-delta modulation part and supplying the generated driving current to a lighting part.

Abstract: There are provided a system on chip (SoC) with a low power mode and a method of driving the SoC, the SoC including: a power part supplying a main clock signal and controlling analog and digital power supply at a normal mode and supplying a sub clock signal and turning analog power off at a low power mode; a radio frequency (RF) part generating the main clock signal at the normal mode and stopping operation at the low power mode, under the control of the power part; and a control part operating according to the main clock signal at the normal mode and operating according to the sub clock signal, under to the control of the power part.

Abstract: A direct sequence spread spectrum (DSSS) transceiver including a DSSS transmitter and a DSSS receiver, wherein the DSSS transmitter includes: an integral code mapping unit mapping source bit data in one of 2N (N is a natural number) of predetermined symbols by N bits and mapping the symbol in one of integral code words that are obtained by previously integrating each of 2N of bi-orthogonal code words; and a radio frequency (RF) transmitting unit transmitting the integral code words mapped by the integral code mapping unit over an RF carrier wave, and the DSSS receiver includes: an RF receiving unit removing an RF carrier wave from an RF signal from the RF transmitting unit and converting an analog signal obtained by removing the RF carrier wave from the RF signal into a digital signal; a differential circuit unit differentiating and converting the digital signal from the RF receiving unit into bi-orthogonal code words; and a symbol detection unit detecting a symbol corresponding to a maximum value of correlat