Patents by Inventor Koon So

Koon So has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080036015
    Abstract: A semiconductor device includes unlined and sealed trenches and methods for forming the unlined and sealed trenches. More particularly, a superjunction semiconductor device includes unlined, and sealed trenches. The trench has sidewalls formed of the semiconductor material. The trench is sealed with a sealing material such that the trench is air-tight. First and second regions are separated by the trench. The first region may include a superjunction Schottky diode or MOSFET. In an alternative embodiment, a plurality of regions are separated by a plurality of unlined and sealed trenches.
    Type: Application
    Filed: August 14, 2007
    Publication date: February 14, 2008
    Applicant: ICEMOS TECHNOLOGY CORPORATION
    Inventors: Samuel Anderson, Koon So
  • Publication number: 20060205174
    Abstract: A method of manufacturing a semiconductor device includes providing semiconductor substrate having trenches and mesas. At least one mesa has first and second sidewalls. The method includes angularly implanting a dopant of a second conductivity into the first sidewall, and angularly implanting a dopant of a second conductivity into the second sidewall. The at least one mesa is converted to a pillar by diffusing the dopants into the at least one mesa. The pillar is then converted to a column by angularly implanting a dopant of the first conductivity into a first sidewall of the pillar, and by angularly implanting the dopant of the first conductivity type into a second sidewall of the pillar. The dopants are then diffused into the pillar to provide a P-N junction of the first and second doped regions located along the depth direction of the adjoining trench. Finally, the trenches are filled with an insulating material.
    Type: Application
    Filed: May 26, 2006
    Publication date: September 14, 2006
    Applicant: THIRD DIMENSION (3D) SEMICONDUCTOR, INC.
    Inventors: Fwu-Iuan Hshieh, Koon So, Brian Pratt
  • Publication number: 20050181564
    Abstract: A method of manufacturing a semiconductor device includes providing semiconductor substrate having trenches and mesas. At least one mesa has first and second sidewalls. The method includes angularly implanting a dopant of a second conductivity into the first sidewall, and angularly implanting a dopant of a second conductivity into the second sidewall. The at least one mesa is converted to a pillar by diffusing the dopants into the at least one mesa. The pillar is then converted to a column by angularly implanting a dopant of the first conductivity into a first sidewall of the pillar, and by angularly implanting the dopant of the first conductivity type into a second sidewall of the pillar. The dopants are then diffused into the pillar to provide a P-N junction of the first and second doped regions located along the depth direction of the adjoining trench. Finally, the trenches are filled with an insulating material.
    Type: Application
    Filed: December 20, 2004
    Publication date: August 18, 2005
    Inventors: Fwu-Iuan Hshieh, Koon So, Brian Pratt
  • Publication number: 20050062075
    Abstract: A trench MOSFET transistor device and a method of making the same.
    Type: Application
    Filed: November 8, 2004
    Publication date: March 24, 2005
    Inventors: Fwu-Iuan Hshieh, Koon So, John Amato, Yan Tsui