Patents by Inventor Korbin Van Dyke
Korbin Van Dyke has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8824819Abstract: An apparatus includes at least one general purpose register and at least one special purpose register and an execution unit that executes at least two instructions in parallel, to decode variable length codes, wherein each of the instructions share use of the at least one general purpose register and the at least one special purpose register. In one example, a processor stores variable length code information among a plurality of general purpose registers and generates decoded variable length code information by decoding the at least one variable length code. The processor also stores the decoded variable length code information among the plurality of general purpose registers.Type: GrantFiled: November 28, 2011Date of Patent: September 2, 2014Assignee: ATI Technologies ULCInventors: Chad E. Fogg, Nital P. Patwa, Parin B. Dalal, Stephen C. Purcell, Korbin Van Dyke, Stephen C. Hale
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Patent number: 8412916Abstract: An integrated circuit also referred to as an integrated computing system has a single substrate that has either deposited thereon or etched thereon, a central processing unit, a north bridge, a south bridge, and a graphics controller. An internal bus is coupled between the north bridge and the central processing unit. The central processing unit and north bridge do not require interfaces to perform bus protocol conversions.Type: GrantFiled: June 24, 2010Date of Patent: April 2, 2013Assignee: ATI Technologies ULCInventors: Adrian Sfarti, Korbin Van Dyke, Michael Frank, Arkadi Avrukin
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Patent number: 8381223Abstract: A method and apparatus for dynamic allocation of processing resources and tasks, including multimedia tasks. Tasks are queued, available processing resources are identified, and the available processing resources are allocated among the tasks. The available processing resources are provided with functional programs corresponding to the tasks. The tasks are performed using available processing resources to produce resulting data, and the resulting data is passed to an input/output device.Type: GrantFiled: July 25, 2011Date of Patent: February 19, 2013Inventors: Korbin Van Dyke, Paul W Campbell, Don A. Van Dyke, Ali Alasti, Stephen C. Purcell
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Publication number: 20120070094Abstract: An apparatus includes at least one general purpose register and at least one special purpose register and an execution unit that executes at least two instructions in parallel, to decode variable length codes, wherein each of the instructions share use of the at least one general purpose register and the at least one special purpose register. In one example, a processor stores variable length code information among a plurality of general purpose registers and generates decoded variable length code information by decoding the at least one variable length code. The processor also stores the decoded variable length code information among the plurality of general purpose registers.Type: ApplicationFiled: November 28, 2011Publication date: March 22, 2012Applicant: ATI TECHNOLOGIES ULCInventors: Chad E. Fogg, Nital P. Patwa, Parin B. Dalal, Stephen C. Purcell, Korbin Van Dyke, Steve C. Hale
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Patent number: 8086055Abstract: An apparatus includes at least one general purpose register and at least one special purpose register and an execution unit that executes at least two instructions in parallel, to decode variable length codes, wherein each of the instructions share use of the at least one general purpose register and the at least one special purpose register. In one example, a processor stores variable length code information among a plurality of general purpose registers and generates decoded variable length code information by decoding the at least one variable length code. The processor also stores the decoded variable length code information among the plurality of general purpose registers.Type: GrantFiled: April 22, 2009Date of Patent: December 27, 2011Assignee: ATI Technologies ULCInventors: Chad E. Fogg, Nital P. Patwa, Parin B. Dalal, Stephen C. Purcell, Korbin Van Dyke, Steve C. Hale
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Publication number: 20110283293Abstract: A method and apparatus for dynamic allocation of processing resources and tasks, including multimedia tasks. Tasks are queued, available processing resources are identified, and the available processing resources are allocated among the tasks. The available processing resources are provided with functional programs corresponding to the tasks. The tasks are performed using available processing resources to produce resulting data, and the resulting data is passed to an input/output device.Type: ApplicationFiled: July 25, 2011Publication date: November 17, 2011Applicant: Advanced Micro Devices, Inc.Inventors: Korbin Van Dyke, Paul Campbell, Don Van Dyke, Ali Alasti, Stephen C. Purcell
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Patent number: 7987465Abstract: A method and apparatus for dynamic allocation of processing resources and tasks, including multimedia tasks. Tasks are queued, available processing resources are identified, and the available processing resources are allocated among the tasks. The available processing resources are provided with functional programs corresponding to the tasks. The tasks are performed using the available processing resources to produce resulting data, and the resulting data is passed to an input/output device.Type: GrantFiled: January 15, 2010Date of Patent: July 26, 2011Assignee: Advanced Micro Devices, Inc.Inventors: Korbin Van Dyke, Paul W Campbell, Don A. Van Dyke, Ali Alasti, Stephen C. Purcell
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Publication number: 20100262746Abstract: An integrated circuit also referred to as an integrated computing system has a single substrate that has either deposited thereon or etched thereon, a central processing unit, a north bridge, a south bridge, and a graphics controller. An internal bus is coupled between the north bridge and the central processing unit. The central processing unit and north bridge do not require interfaces to perform bus protocol conversions.Type: ApplicationFiled: June 24, 2010Publication date: October 14, 2010Applicant: ATI TECHNOLOGIES ULCInventors: Adrian Sfarti, Korbin Van Dyke, Michael Frank, Arkadi Avrukin
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Publication number: 20100208826Abstract: A method that decodes serially received MPEG variable length codes by executing instructions in parallel. The method includes an execution unit, which includes multiple pipelined functional units. The functional units execute at least two of the instructions in parallel. The instructions utilize and share general purpose registers. The general purpose registers store information used by at least two of the instructions.Type: ApplicationFiled: April 22, 2009Publication date: August 19, 2010Applicant: ATI International SRLInventors: Chad E. Fogg, Nital P. Patwa, Parin B. Dalal, Stephen C. Purcell, Korbin Van Dyke, Steve C. Hale
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Patent number: 7769988Abstract: A method of integrating a personal computing system and apparatus thereof include processing that begins by integrating a central processing unit with a North bridge on a single substrate such that the central processing unit is directly coupled to the North bridge via an internal bus. The processing then continues by providing memory access requests from the central processing unit to the North bridge at a rate of the central processing unit. The processing continues by having the North bridge buffer the memory access request and subsequently process the memory access requests at a rate of the memory. The method may be expanded by integrating a South bridge onto the same substrate as well as integrating system memory onto the same substrate.Type: GrantFiled: December 23, 1999Date of Patent: August 3, 2010Assignee: ATI Technologies ULCInventors: Adrian Sfarti, Korbin Van Dyke, Michael Frank, Arkadi Avrukin
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Publication number: 20100122262Abstract: A method and apparatus for dynamic allocation of processing resources and tasks, including multimedia tasks. Tasks are queued, available processing resources are identified, and the available processing resources are allocated among the tasks. The available processing resources are provided with functional programs corresponding to the tasks. The tasks are performed using the available processing resources to produce resulting data, and the resulting data is passed to an input/output device.Type: ApplicationFiled: January 15, 2010Publication date: May 13, 2010Applicant: Advanced Micro Devices, Inc.Inventors: Korbin Van Dyke, Paul Campbell, Don Van Dyke, Ali Alasti, Stephen C. Purcell
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Patent number: 7661107Abstract: A method and apparatus for dynamic allocation of processing resources and tasks, including multimedia tasks. Tasks are queued, available processing resources are identified, and the available processing resources are allocated among the tasks. The available processing resources are provided with functional programs corresponding to the tasks. The tasks are performed using the available processing resources to produce resulting data, and the resulting data is passed to an input/output device.Type: GrantFiled: January 18, 2000Date of Patent: February 9, 2010Assignee: Advanced Micro Devices, Inc.Inventors: Korbin Van Dyke, Paul Campbell, Don A. Van Dyke, Ali Alasti, Stephen C. Purcell
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Patent number: 7574065Abstract: A method that decodes serially received MPEG variable length codes by executing instructions in parallel. The method includes an execution unit which includes multiple pipelined functional units. The functional units execute at least two of the instructions in parallel. The instructions utilize and share general purpose registers. The general purpose registers store information used by at least two of the instructions.Type: GrantFiled: June 10, 2004Date of Patent: August 11, 2009Assignee: ATI International SRLInventors: Chad E. Fogg, Nital P. Patwa, Parin B. Dalal, Stephen C. Purcell, Korbin Van Dyke, Steve C. Hale
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Publication number: 20070255894Abstract: A vector processing system provides high performance vector processing using a System-On-a-Chip (SOC) implementation technique. One or more scalar processors (or cores) operate in conjunction with a vector processor, and the processors collectively share access to a plurality of memory interfaces coupled to Dynamic Random Access read/write Memories (DRAMs). In typical embodiments the vector processor operates as a slave to the scalar processors, executing computationally intensive Single Instruction Multiple Data (SIMD) codes in response to commands received from the scalar processors. The vector processor implements a vector processing Instruction Set Architecture (ISA) including machine state, instruction set, exception model, and memory model.Type: ApplicationFiled: February 10, 2006Publication date: November 1, 2007Inventors: Richard Hessel, Nathan Tuck, Korbin Van Dyke, Chetana Keltcher
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Patent number: 7254231Abstract: A structure and associated method to implement encryption/decryption under the Data Encryption Standard (DES). Several additional instructions are included in the instruction set of a general purpose microprocessor to operate in conjunction with hardware included in a data path of the general purpose microprocessor. The additional instructions perform a portion of the DES algorithm, in particular, a portion of a DES round. The state information used at each step of the encryption portion of the DES algorithm is provided in various general purpose registers of the general purpose microprocessor. In one embodiment, all sixteen subkeys are selected prior to the DES step in the general processor after a DES key is known. In another embodiment, each subkey is selected during the round it is used. In yet another embodiment, each subkey is selected during the round it is used, as part of an additional instruction executed by the general purpose microprocessor.Type: GrantFiled: October 14, 1999Date of Patent: August 7, 2007Assignee: ATI International SRLInventors: Don Van Dyke, Korbin Van Dyke, Stephen C. Purcell
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Publication number: 20050086650Abstract: A computer has instruction pipeline circuitry capable of executing two instruction set architectures (ISA's). A binary translator translates at least a selected portion of a computer program from a lower-performance one of the ISA's to a higher-performance one of the ISA's. Hardware initiates a query when about to execute a program region coded in the lower-performance ISA, to determine whether a higher-performance translation exists. If so, the about-to-be-executed instruction is aborted, and control transfers to the higher-performance translation. After execution of the higher-performance translation, execution of the lower-performance region is reestablished at a point downstream from the aborted instruction, in a context logically equivalent to that which would have prevailed had the code of the lower-performance region been allowed to proceed.Type: ApplicationFiled: December 2, 2004Publication date: April 21, 2005Applicant: ATI International SRLInventors: John Yates, David Reese, Paul Hohensee, Stephen Purcell, Korbin Van Dyke
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Publication number: 20050086451Abstract: A microprocessor chip has instruction pipeline circuitry, and instruction classification circuitry that classifies instructions as they are executed into a small number of classes and records a classification code value. An on-chip table has entries corresponding to a range of addresses of a memory and designed to hold a statistical assessment of a value of consulting an off-chip table in a memory of the computer. Lookup circuitry is designed to fetch an entry from the on-chip table as part of the basic instruction processing cycle of the microprocessor. A mask has a value set at least in part by a timer. The instruction pipeline circuitry is controlled based on the value of the on-chip table entry corresponding to the address of instructions processed, the current value of the mask, the recorded classification code, and the off-chip table.Type: ApplicationFiled: December 2, 2004Publication date: April 21, 2005Applicant: ATI International SRLInventors: John Yates, David Reese, Paul Hohensee, Korbin Van Dyke, Shalesh Thusoo, T.R. Ramesh
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Patent number: 6775414Abstract: A method that decodes serially received MPEG variable length codes by executing instructions in parallel. The method includes an execution unit which includes multiple pipelined functional units. The functional units execute at least two of the instructions in parallel. The instructions utilize and share general purpose registers. The general purpose registers store information used by at least two of the instructions.Type: GrantFiled: November 19, 1999Date of Patent: August 10, 2004Assignee: ATI International SRLInventors: Chad E. Fogg, Nital P. Patwa, Parin B. Dalal, Stephen C. Purcell, Korbin Van Dyke, Steve C. Hale
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Patent number: 6745318Abstract: An apparatus that provides configurable processing includes a fetch module, a decoder, and a dynamic arithmetic unit. The fetch module is operable to fetch at least one instruction and provide it to the decoder. The decoder receives the instruction and decodes it. The dynamic arithmetic logic unit receives the decoded instruction and configures at least one configurable arithmetic logic unit to perform an operation contained within the decoded instruction.Type: GrantFiled: August 18, 1999Date of Patent: June 1, 2004Inventors: Sanjay Mansingh, Niteen Patkar, Korbin Van Dyke, Stephen Hale, Dee Tovey, Nital Patwa, Stephen C. Purcell
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Patent number: 6651159Abstract: A floating point register stack for a processor combines a plurality of two general purpose registers to form a register stack for x86 instructions and leaves the remaining general purpose registers for native instructions of the processor. By mapping x86 sources into the stack of two general purpose registers and operating x86 instructions on the x86 stack, the register stack for the processor is able to support both the processor's native instruction set and the x86 instruction set without increasing the size of the register stack.Type: GrantFiled: November 29, 1999Date of Patent: November 18, 2003Assignee: ATI International SRLInventors: Tiruvur R. Ramesh, Sanjay Mansingh, Korbin Van Dyke