Patents by Inventor Koreaki Fujita
Koreaki Fujita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 5612917Abstract: A dynamic random access memory includes memory cell array blocks, row decoders, redundant word lines, redundant memory cells, replacement circuits, and a normal memory cell de-select circuit. Each memory cell array block includes normal word lines and normal memory cells. Each row decoder is provided corresponding to one memory cell array block. Any of the redundant word line is provided corresponding to one memory cell array block. Each replacement circuit includes a redundancy select circuit, a replacement address program circuit, and a redundant word line select circuit. The redundancy select circuit has set in advance whether a corresponding redundant word line is to be used or not. The program circuit has an address programmed of a normal word line to be replaced with a corresponding redundant word line. The normal memory cell de-select circuit inactivates a row decoder in response to an output of the replacement circuit when any replacement circuit selects a corresponding redundant word line.Type: GrantFiled: April 5, 1995Date of Patent: March 18, 1997Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Kunihiko Kozaru, Koreaki Fujita
-
Patent number: 5446692Abstract: An improved SRAM is disclosed including a plurality of memory blocks each having a redundancy memory cell to be shared. In redundancy row decoders 50a, 50b, 50c provided in each memory block, a memory block to be remedied is programmed. Accordingly, a redundancy memory cell row corresponding to each redundancy row decoder can be used for remedy of a defect memory cell in another memory block. Since a defect memory cell may be remedied flexibly, the yield rate in production of semiconductor memories is improved.Type: GrantFiled: January 25, 1993Date of Patent: August 29, 1995Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Yoshiyuki Haraguchi, Koreaki Fujita, Kiyoyasu Akai
-
Patent number: 5416740Abstract: An SRAM disclosed herein includes 64 memory cell array blocks and a redundant memory cell array block. The redundant memory cell array includes a total of 16 redundant memory cell columns. A defect address indicating a location of a defective memory column is programmed in an address programming circuit, and the specific defecting column in the defect address is programmed in an I/O programming circuit. Although each memory cell does not include a spare memory cell column or row for redundancy, the defect can be repaired by using a redundant memory cell array, so that the high integration of the SRAM can be accomplished.Type: GrantFiled: December 9, 1992Date of Patent: May 16, 1995Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Koreaki Fujita, Masayuki Yamashita, Masamitsu Shimasaki
-
Patent number: 5392247Abstract: An addressing system of redundancy word lines is provided independently of an addressing system of word lines in memory cell array blocks. Outputs of substitution circuits including redundancy selecting circuits and substitute address program circuits are applied as redundancy word line activating signals directly to the redundancy word lines not through decoders, respectively. An output of a normal memory cell nonselecting circuit is applied as a decoder inactivating signal to the decoders.Type: GrantFiled: June 6, 1994Date of Patent: February 21, 1995Assignee: Mitsubishi Denki Kabushiki KaishaInventor: Koreaki Fujita
-
Patent number: 5379259Abstract: Two redundant blocks RB1 and RB2 are provided independent from the normal memory cell block BL, and selection of the redundant block when redundancy is selected is carried out by a least significant column address signal Y0 and a signal /Y0 complementary thereto in a semiconductor memory device. Therefore, a semiconductor memory device can be provided in which when defective bits exist continuously in a memory cell array, the continuous defective bit can be replaced by two redundant bit lines.Type: GrantFiled: March 1, 1993Date of Patent: January 3, 1995Assignee: Mitsubishi Denki Kabushiki KaishaInventor: Koreaki Fujita
-
Patent number: 5282175Abstract: In a SRAM of a selected word line structure, each local decoder is connected to a corresponding main word line and a corresponding Z decoder signal line. Each local decoder includes a circuit including two MOS transistors connected in series to each other which circuit has one end grounded. The corresponding local word line is connected to a node between these two transistors. Out of the corresponding main word line and the corresponding Z decoder signal line, one is connected to the gates of these transistors and the other is connected to the other end of said circuit, which the other end is not grounded. The potential on the corresponding local word line attains a high level only when the potential on the signal line connected to the gate of these two transistors, is at a logical level at which the transistor can be turned on and the potential on said one signal line is at a high level.Type: GrantFiled: May 24, 1991Date of Patent: January 25, 1994Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Koreaki Fujita, Shuji Murakami, Kenji Anami
-
Patent number: 5063305Abstract: In a MOS transistor circuit (comprising a pair of current mirror circuits, each comprising: first and second MOS transistors having their gate electrodes connected together third and fourth MOS transistors respectively connected in series with the first and second transistors, the third and the fourth MOS transistors of the pair of current mirror circuits receiving a pair of complementary signals at their gate electrodes; and the nodes between the second and the fourth MOS transistors forming output nodes of the current mirror circuits), a pair of capacitors each coupling the output of one current mirror circuit to the gate electrodes of the first and the second MOS transistors of the other current mirror circuit. This provides positive feedback. The change in the outputs responsive to change in the inputs is thereby accelerated.Type: GrantFiled: April 14, 1989Date of Patent: November 5, 1991Assignee: Mitsubishi Denki Kabushik KaishaInventors: Hiroshi Minami, Koreaki Fujita
-
Patent number: 4907201Abstract: In a MOS transistor circuit (comprising a pair of current mirror circuits, each comprising: first and second MOS transistors having their gate electrodes connected together third and fourth MOS transistors respectively connected in series with the first and second transistors, the third and the fourth MOS transistors of the pair of current mirror circuits receiving a pair of complementary signals at their gate electrodes; and the nodes between the second and the fourth MOS transistors forming output nodes of the current mirror circuit), a pair of capacitors each coupling the output of one current mirror circuit to the gate electrodes of the first and the second MOS transistors of the other current mirror circuit. This provides positive feedback. The change in the outputs responsive to change in the inputs is thereby accelerated.Type: GrantFiled: July 14, 1988Date of Patent: March 6, 1990Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Hiroshi Minami, Koreaki Fujita
-
Patent number: 4767942Abstract: In a MOS transistor circuit (comprising a pair of current mirror circuits, each comprising: first and second MOS transistors having their gate electrodes connected together; third and fourth MOS transistors respectively connected in series with the first and second transistors the third and the fourth MOS transistors of the pair of current mirror circuits receiving a pair of complementary signals at their gate electrodes; and the nodes between the second and the fourth MOS transistors forming output nodes of the current mirror circuits), a pair of capacitors each coupling the output of one current mirror circuit to the gate electrodes of the first and the second MOS transistors of the other current mirror circuit. This provides positive feedback. The change in the outputs responsive to change in the inputs is thereby accelerated.Type: GrantFiled: May 6, 1987Date of Patent: August 30, 1988Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Hiroshi Minami, Koreaki Fujita