Patents by Inventor Korekiyo ITO

Korekiyo ITO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240072107
    Abstract: A semiconductor device that includes a substrate; a first electrode layer on the substrate; a dielectric film on the first electrode layer; a second electrode layer on the dielectric film; a protective layer covering the first electrode layer and the second electrode layer; and an outer electrode penetrating the protective layer. The dielectric film includes silicon nitride, and an atomic concentration ratio of Si to a total amount of Si and N contained in the dielectric film is 43 atom % to 70 atom %.
    Type: Application
    Filed: November 6, 2023
    Publication date: February 29, 2024
    Inventors: Masatomi HARADA, Korekiyo ITO, Takeshi KAGAWA
  • Publication number: 20240071687
    Abstract: A semiconductor device that includes: a substrate having a first main surface and a second main surface opposite to each other in a thickness direction; a circuit layer on the first main surface of the substrate, the circuit layer having a first electrode layer, a second electrode layer, a dielectric layer between the first electrode layer and the second electrode layer, a first outer electrode and a second outer electrode each extending to a surface of the circuit layer opposite to the substrate; and a first resin body at each of four corners of the substrate in a plan view in the thickness direction, and wherein, in the thickness direction, a top end of the first resin body on the side opposite to the substrate is positioned higher than top ends of the first outer electrode and the second outer electrode on the side opposite to the substrate.
    Type: Application
    Filed: November 6, 2023
    Publication date: February 29, 2024
    Inventors: Korekiyo ITO, Masatomi HARADA, Yuta IMAMURA
  • Publication number: 20240063224
    Abstract: A support substrate for a passive electronic component, the support substrate including: a semiconductor substrate; a charge trap layer on the semiconductor substrate and having a higher crystal defect density than the semiconductor substrate; and an insulating layer on the charge trap layer. In a first aspect, the insulating layer is composed of silicon nitride, and an atomic concentration ratio of N to a total amount of Si and N in the insulating layer is not greater than 45 atom %. In a second aspect, the insulating layer includes a first insulating layer on the charge trap layer; and a second insulating layer on the first insulating layer, wherein a first fixed charge within the first insulating layer and a second fixed charge within the second insulating layer have opposite polarities, and the first insulating layer has a thickness of not less than 0.5 nm and not greater than 3 nm.
    Type: Application
    Filed: October 30, 2023
    Publication date: February 22, 2024
    Inventors: Korekiyo ITO, Masatomi HARADA
  • Publication number: 20240062958
    Abstract: A capacitor that includes: a substrate; a first electrode layer on the substrate, the first electrode layer including a first principal surface facing the substrate, and a second principal surface opposite the first principal surface; a dielectric film on the first electrode layer and covering an end portion of the first electrode layer; a second electrode layer on the dielectric film, the second electrode layer including a third principal surface facing the dielectric film, a fourth principal surface opposite the third principal surface, and a side surface joining the third principal surface and the fourth principal surface, wherein at least part of the side surface of the second electrode layer has a tapered shape which is inclined inward from the third principal surface to the fourth principal surface.
    Type: Application
    Filed: October 30, 2023
    Publication date: February 22, 2024
    Inventors: Masatomi HARADA, Korekiyo ITO, Takeshi KAGAWA, Yuta IMAMURA
  • Publication number: 20240063252
    Abstract: A semiconductor device that includes: a substrate having a first main surface and a second main surface opposite to each other in a thickness direction; a circuit layer on the first main surface of the substrate; and a first resin body between an end portion of the substrate and the first outer electrode, and between the end portion of the substrate and the second outer electrode in a plan view in the thickness direction. In the thickness direction, a leading end of the first resin body is positioned higher than top ends of the first and second outer electrodes. In a sectional view, a first side surface of the first resin body approaches a second side surface of the first resin body on a side close to the end portion of the substrate, and the second side surface rises steeply against a first main surface of the substrate.
    Type: Application
    Filed: October 30, 2023
    Publication date: February 22, 2024
    Inventors: Yuta IMAMURA, Masatomi HARADA, Takeshi KAGAWA, Korekiyo ITO
  • Publication number: 20210382123
    Abstract: A magneto-resistive element includes a first element section including a first unit element and a second element section including a second unit element. The first element section is connected to the second element section in series. The first unit element includes a first reference layer with a magnetization that is fixed in an in-plane direction, and a first free layer including a vortex magnetization. The second unit element includes a second reference layer with a magnetization that is fixed in an in-plane direction, and a second free layer including a vortex magnetization. A direction of the fixed magnetization of the first reference layer is opposite to that of the second reference layer.
    Type: Application
    Filed: August 19, 2021
    Publication date: December 9, 2021
    Inventors: Masashi KUBOTA, Korekiyo ITO
  • Patent number: 10707406
    Abstract: In a method of manufacturing a piezoelectric device, during an isolation formation step, a supporting substrate has a piezoelectric thin film formed on its front with a compressive stress film present on its back. The compressive stress film compresses the surface on a piezoelectric single crystal substrate side of the supporting substrate, and the piezoelectric thin film compresses the back of the supporting substrate, which is opposite to the surface on the piezoelectric single crystal substrate side. Thus, the compressive stress produced by the compressive stress film and that produced by the piezoelectric thin film are balanced in the supporting substrate, which causes the supporting substrate to be free of warpage and remain flat. A driving force that induces isolation in the isolation formation step is gasification of the implanted ionized element rather than the compressive stress to the isolation plane produced by the piezoelectric thin film.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: July 7, 2020
    Assignee: MURATA MANUFACTURING CO., LTD
    Inventor: Korekiyo Ito
  • Patent number: 10553778
    Abstract: In a method of manufacturing a piezoelectric device, among a +C plane on a +Z axis side of a piezoelectric thin film and a ?C plane on a ?Z axis side of the piezoelectric thin film, the ?C plane on the ?Z axis side of the piezoelectric thin film is etched. Thus, ?Z planes of the piezoelectric thin film on which epitaxial growth is possible are exposed. Ti is epitaxially grown on the ?Z planes of the piezoelectric thin film in the ?Z axis direction such that the crystal growth plane thereof is parallel to the ?Z planes of the piezoelectric thin film. Al is then epitaxially grown on the surface of the Ti electrode in the ?Z axis direction such that the crystal growth plane thereof is parallel to the ?Z planes of the piezoelectric thin film.
    Type: Grant
    Filed: November 10, 2016
    Date of Patent: February 4, 2020
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Korekiyo Ito, Takashi Iwamoto
  • Patent number: 10447240
    Abstract: An elastic wave device includes IDT electrodes stacked on a piezoelectric thin film. The IDT electrode includes a plurality of first electrode fingers and a plurality of second electrode fingers. A line connecting the distal ends of the first electrode fingers or the distal ends of the second electrode fingers extends obliquely with respect to a propagation direction of an elastic wave at an oblique angle ?. The oblique angle ? is about 0.4° or more and about 10° or less.
    Type: Grant
    Filed: June 20, 2016
    Date of Patent: October 15, 2019
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Takashi Yamane, Hideki Iwamoto, Keiji Okada, Syunsuke Kido, Masanori Otagawa, Ippei Hatsuda, Korekiyo Ito
  • Publication number: 20170200882
    Abstract: In a method of manufacturing a piezoelectric device, during an isolation formation step, a supporting substrate has a piezoelectric thin film formed on its front with a compressive stress film present on its back. The compressive stress film compresses the surface on a piezoelectric single crystal substrate side of the supporting substrate, and the piezoelectric thin film compresses the back of the supporting substrate, which is opposite to the surface on the piezoelectric single crystal substrate side. Thus, the compressive stress produced by the compressive stress film and that produced by the piezoelectric thin film are balanced in the supporting substrate, which causes the supporting substrate to be free of warpage and remain flat. A driving force that induces isolation in the isolation formation step is gasification of the implanted ionized element rather than the compressive stress to the isolation plane produced by the piezoelectric thin film.
    Type: Application
    Filed: March 30, 2017
    Publication date: July 13, 2017
    Inventor: Korekiyo ITO
  • Patent number: 9647199
    Abstract: In a method of manufacturing a piezoelectric device, during an isolation formation step, a supporting substrate has a piezoelectric thin film formed on its front with a compressive stress film present on its back. The compressive stress film compresses the surface on a piezoelectric single crystal substrate side of the supporting substrate, and the piezoelectric thin film compresses the back of the supporting substrate, which is opposite to the surface on the piezoelectric single crystal substrate side. Thus, the compressive stress produced by the compressive stress film and that produced by the piezoelectric thin film are balanced in the supporting substrate, which causes the supporting substrate to be free of warpage and remain flat. A driving force that induces isolation in the isolation formation step is gasification of the implanted ionized element rather than the compressive stress to the isolation plane produced by the piezoelectric thin film.
    Type: Grant
    Filed: March 26, 2013
    Date of Patent: May 9, 2017
    Assignee: Murata Manufacturing Co., Ltd.
    Inventor: Korekiyo Ito
  • Publication number: 20170062698
    Abstract: In a method of manufacturing a piezoelectric device, among a +C plane on a +Z axis side of a piezoelectric thin film and a ?C plane on a ?Z axis side of the piezoelectric thin film, the ?C plane on the ?Z axis side of the piezoelectric thin film is etched. Thus, ?Z planes of the piezoelectric thin film on which epitaxial growth is possible are exposed. Ti is epitaxially grown on the ?Z planes of the piezoelectric thin film in the ?Z axis direction such that the crystal growth plane thereof is parallel to the ?Z planes of the piezoelectric thin film. Al is then epitaxially grown on the surface of the Ti electrode in the ?Z axis direction such that the crystal growth plane thereof is parallel to the ?Z planes of the piezoelectric thin film.
    Type: Application
    Filed: November 10, 2016
    Publication date: March 2, 2017
    Inventors: Korekiyo ITO, Takashi IWAMOTO
  • Patent number: 9537079
    Abstract: In a method of manufacturing a piezoelectric device, among a +C plane on a +Z axis side of a piezoelectric thin film and a ?C plane on a ?Z axis side of the piezoelectric thin film, the ?C plane on the ?Z axis side of the piezoelectric thin film is etched. Thus, ?Z planes of the piezoelectric thin film on which epitaxial growth is possible are exposed. Ti is epitaxially grown on the ?Z planes of the piezoelectric thin film in the ?Z axis direction such that the crystal growth plane thereof is parallel to the ?Z planes of the piezoelectric thin film. Al is then epitaxially grown on the surface of the Ti electrode in the ?Z axis direction such that the crystal growth plane thereof is parallel to the ?Z planes of the piezoelectric thin film.
    Type: Grant
    Filed: September 17, 2013
    Date of Patent: January 3, 2017
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Korekiyo Ito, Takashi Iwamoto
  • Publication number: 20160294361
    Abstract: An elastic wave device includes IDT electrodes stacked on a piezoelectric thin film. The IDT electrode includes a plurality of first electrode fingers and a plurality of second electrode fingers. A line connecting the distal ends of the first electrode fingers or the distal ends of the second electrode fingers extends obliquely with respect to a propagation direction of an elastic wave at an oblique angle ?. The oblique angle ? is about 0.4° or more and about 10° or less.
    Type: Application
    Filed: June 20, 2016
    Publication date: October 6, 2016
    Inventors: Takashi YAMANE, Hideki IWAMOTO, Keiji OKADA, Syunsuke KIDO, Masanori OTAGAWA, Ippei HATSUDA, Korekiyo ITO
  • Patent number: 9240540
    Abstract: In a piezoelectric device and a method of manufacturing thereof, after an ion implanted portion is formed in a piezoelectric single crystal substrate by implantation of hydrogen ions, an interlayer of a metal is formed on a rear surface of the piezoelectric single crystal substrate. In addition, a support member is bonded to the piezoelectric single crystal substrate with the interlayer interposed therebetween. A composite piezoelectric body in which the ion implanted portion is formed is heated at about 450° C. to about 700° C. to oxidize the metal of the interlayer so as to decrease the conductivity thereof. Accordingly, the conductivity of the interlayer is decreased, so that a piezoelectric device having excellent resonance characteristics is provided.
    Type: Grant
    Filed: November 5, 2013
    Date of Patent: January 19, 2016
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Korekiyo Ito
  • Publication number: 20140191619
    Abstract: In a method of manufacturing a piezoelectric device, among a +C plane on a +Z axis side of a piezoelectric thin film and a ?C plane on a ?Z axis side of the piezoelectric thin film, the ?C plane on the ?Z axis side of the piezoelectric thin film is etched. Thus, ?Z planes of the piezoelectric thin film on which epitaxial growth is possible are exposed. Ti is epitaxially grown on the ?Z planes of the piezoelectric thin film in the ?Z axis direction such that the crystal growth plane thereof is parallel to the ?Z planes of the piezoelectric thin film. Al is then epitaxially grown on the surface of the Ti electrode in the ?Z axis direction such that the crystal growth plane thereof is parallel to the ?Z planes of the piezoelectric thin film.
    Type: Application
    Filed: September 17, 2013
    Publication date: July 10, 2014
    Applicant: MURATA MANUFACTURING CO., LTD.
    Inventors: Korekiyo ITO, Takashi IWAMOTO
  • Publication number: 20140055008
    Abstract: In a piezoelectric device and a method of manufacturing thereof, after an ion implanted portion is formed in a piezoelectric single crystal substrate by implantation of hydrogen ions, an interlayer of a metal is formed on a rear surface of the piezoelectric single crystal substrate. In addition, a support member is bonded to the piezoelectric single crystal substrate with the interlayer interposed therebetween. A composite piezoelectric body in which the ion implanted portion is formed is heated at about 450° C. to about 700° C. to oxidize the metal of the interlayer so as to decrease the conductivity thereof. Accordingly, the conductivity of the interlayer is decreased, so that a piezoelectric device having excellent resonance characteristics is provided.
    Type: Application
    Filed: November 5, 2013
    Publication date: February 27, 2014
    Applicant: MURATA MANUFACTURING CO., LTD.
    Inventor: Korekiyo ITO
  • Patent number: 8601657
    Abstract: In a piezoelectric device and a method of manufacturing thereof, after an ion implanted portion is formed in a piezoelectric single crystal substrate by implantation of hydrogen ions, an interlayer of a metal is formed on a rear surface of the piezoelectric single crystal substrate. In addition, a support member is bonded to the piezoelectric single crystal substrate with the interlayer interposed therebetween. A composite piezoelectric body in which the ion implanted portion is formed is heated at about 450° C. to about 700° C. to oxidize the metal of the interlayer so as to decrease the conductivity thereof. Accordingly, the conductivity of the interlayer is decreased, so that a piezoelectric device having excellent resonance characteristics is provided.
    Type: Grant
    Filed: May 17, 2012
    Date of Patent: December 10, 2013
    Assignee: Murata Manufacturing Co., Ltd.
    Inventor: Korekiyo Ito
  • Publication number: 20120229003
    Abstract: In a piezoelectric device and a method of manufacturing thereof, after an ion implanted portion is formed in a piezoelectric single crystal substrate by implantation of hydrogen ions, an interlayer of a metal is formed on a rear surface of the piezoelectric single crystal substrate. In addition, a support member is bonded to the piezoelectric single crystal substrate with the interlayer interposed therebetween. A composite piezoelectric body in which the ion implanted portion is formed is heated at about 450° C. to about 700° C. to oxidize the metal of the interlayer so as to decrease the conductivity thereof. Accordingly, the conductivity of the interlayer is decreased, so that a piezoelectric device having excellent resonance characteristics is provided.
    Type: Application
    Filed: May 17, 2012
    Publication date: September 13, 2012
    Applicant: MURATA MANUFACTURING CO., LTD.
    Inventor: Korekiyo ITO