Abstract: A semiconductor device comprises a DSP (Digital Signal Processor), a CPU for controlling the DSP and an interface circuit. The interface circuit comprises an input circuit, a gain-adjusting circuit and an output circuit. The input circuit inputs a digital signal and supplies the signal to the DSP synchronously with a first clock signal. The gain-adjusting circuit is capable of adjusting the gain of the digital signal supplied to the input circuit. The output circuit adds a digital signal received from the DSP to the digital signal with the gain thereof adjusted and outputs a signal obtained as a result of the addition synchronously with the first clock signal. A signal path extended from the input circuit through the gain-adjusting circuit to the output circuit forms hardware. A digital signal to be transmitted propagates through the hardware to be subjected to the so-called side-tone processing.

Abstract: A semiconductor device comprises a DSP (Digital Signal Processor), a CPU for controlling the DSP and an interface circuit. The interface circuit comprises an input circuit, a gain-adjusting circuit and an output circuit. The input circuit inputs a digital signal and supplies the signal to the DSP synchronously with a first clock signal. The gain-adjusting circuit is capable of adjusting the gain of the digital signal supplied to the input circuit. The output circuit adds a digital signal received from the DSP to the digital signal with the gain thereof adjusted and outputs a signal obtained as a result of the addition synchronously with the first clock signal. A signal path extended from the input circuit through the gain-adjusting circuit to the output circuit forms hardware. A digital signal to be transmitted propagates through the hardware to be subjected to the so-called side-tone processing.

Abstract: A data transfer controller is provided which can reduce a CPU control load necessary for data transfer cyclically using a plurality of data transfer areas. A DMAC constituting the data transfer controller is initially set with a transfer start address of a transfer source or transfer destination by a CPU, issues an interrupt to CPU each time the data transfer responding to a transfer request from the transfer source reaches a predetermined data amount based upon the transfer start address, and initializes an address of the transfer source or transfer destination to the transfer start address each time the interrupt is issued predetermined plural times. After CPU sets once the data transfer conditions to DMAC, CPU can continue data processing by repetitively using a limited number of memory areas, without performing any process of repetitively setting the data transfer conditions necessary for a data transfer control for receiving voice data.

Abstract: A cordless telephone apparatus has a base station connected to a public telephone network and assigned with a specific identification code and one or more personal stations linked to the base station through the medium of radio frequencies. The base station has one or more additional functions in addition to the speech function. The personal station can perform radio communications with the base station within a range in which radio waves from the base station is receivable and can perform radio communications with a cell station connected to a public telephone network outside the radio wave receivable range. The personal station has a remote-control instruction unit for instructing operation of the additional function of the base station.