Abstract: An NPC inverter control system includes a DC power source having a neutral point corresponding to a junction of a pair of capacitors connected in serial one another, a positive electrode and a negative electrode, at least one multi-level inverter circuit having a plurality of semiconductor devices coupled to the DC power source and configured to invert the DC power to an AC power and to supply the AC power to a load, and a plurality of saturatable reactors configured to join the positive and negative electrodes of the DC power source to the multi-level inverter circuit.

Abstract: A gate control circuit for turning on and off an insulated gate semiconductor device having gate, emitter and collector terminals, including a first DC power source coupled to the gate terminal via a first switch and configured to apply a positive voltage to the gate terminal in order to turn on the insulated gate semiconductor device when the first switch is turned on and the second switch is turned off; a second DC power source coupled to the gate terminal via a second switch and configured to apply a negative voltage to the gate terminal in order to turn off the insulated gate semiconductor device when the second switch is turned on and the first switch is turned off; a parallel circuit of a diode and a capacitor coupled in series to the second switch; and a turn off assist circuit configured to produce a negative charge on the capacitor to assist in turning off the insulated gate semiconductor device.

Abstract: A power converter apparatus, including a DC power source, a semiconductor stack, connected to the DC power source in parallel, having a plurality of semiconductor devices and a cooler for refrigerating the semiconductor devices, the semiconductor devices and the cooler are stacked and pressured to each other, and a snubber circuit, connected to the DC power source in parallel, having a serial circuit of a capacitor and a diode, and a resistor connected in parallel to the diode, one terminal of the capacitor is disposed adjacent to the semiconductor stack so that magnetic flux generated by current flowing in the terminal cancels magnetic flux caused by current flowing in the semiconductor stack.

Abstract: A multiple inverter system of the present invention is disclosed. It includes a plurality of input transformers having secondary windings and a plurality of unit inverter cells connected in series at n stages to compose respective phases and supply the electric power to a multiple phase load in combination with the input transformers. The input transformers have 3n sets of three-phase windings at the secondary side and the secondary windings of the transformers, which are out-of-phase at each phase, are connected to unit inverter cells of each phase at the n-th stages. Further, the present invention is provided with a bypass switch control to melt a fuse that is applicable to a unit inverter given with a circuit closing command by giving this circuit closing command to a bypass switch corresponding to applicable unit inverters in response to an operation abnormality detector and a DC abnormality detector.

Abstract: A power converter having at least a pair of voltage drive switching elements, which comprises a gate control circuit, the gate control circuit comprising a detecting section for detecting at least one of a set of device parameters and a set of electric parameters of the voltage drive switching elements, a monitoring section for monitoring at least one of states of turn-on and turn-off of the voltage drive switching elements based on the at least one of a set of device parameters and a set of electric parameters of the voltage drive switching elements detected by the detecting section, and a control section for controlling a gate of the voltage drive switching elements based on a monitoring result of the monitoring section.

Abstract: A neutral point clamped (NPC) inverter control system including a DC power source to output DC voltage having a neutral point, an NPC inverter to convert the DC voltage into AC voltage in three phases through a PWM control, a mode selecting unit to decide a first and a second PWM modes by comparing amplitude of voltage reference with a prescribed value that is defined by a minimum pulse width, a first voltage reference conversion means to add a prescribed bias value at which a polarity changes to positive/negative within a fixed period to secure the minimum pulse width to voltage references in respective phases in a first PWM mode, a second voltage reference conversion means to fix the voltage reference in one phase by a value that secures the minimum pulse width when voltage reference in one phase is smaller than a prescribed value that is defined by the minimum pulse width in a second PWM mode and correct voltage references of other two phases so as to make line voltage to a value corresponding to the volta

Abstract: A power converter including a plurality of serially connected self-turn-off semiconductor elements, including a first control circuit for producing a plurality of control signals, and a plurality of second control circuits is connected to receive respective of the control signals to supply a non-conduction control signal to a respective of the self-turn-off semiconductor elements to turn off the respective semiconductor element. The power converter further includes a plurality of failure detectors and blocking circuits. Each of the failure detectors is connected to a respective of the self-turn-off semiconductor elements for detecting a fault thereof to produce a fault detection signal when the respective self-turn-off semiconductor elements has failed. Each of the blocking circuits is connected to the respective failure detector and to the first control circuit for blocking either the respective control signal or the respective non-conduction control signal based on the respective fault detection signal.