Abstract: An interleave control which accesses a plurality of memory elements. A logical address is converted into a real address composed of a memory element selection address and a memory element address. The logical address of a CPU that has a logical address space divided into N area is converted into the real address decided in a way number W, and the memory elements are accessed by the interleave control. A real address area utilization information is prepared that is common to all the way numbers by dividing the real address space formed of a plurality of memory elements into areas (N×Wmax) based upon multiplying the area number N of the logical address space and the maximum way number Wmax, and utilization prohibition information is recorded in the area including the abnormal portion of the real address area utilization information when the abnormality of the memory element is detected.

Abstract: A plurality of memory elements is converted by a real address formed of an element selection address and a memory element address into a real address deciding the logic address of a CPU utilizing a logic address space divided into N areas by way number W, and is accessed by an interleave control. A real address area utilization table common to all the way numbers recorded with utilizable information by dividing the real address space formed of a plurality of memory elements into the areas (N×Wmax) multiplying the area number N of the CPU logic address space by the maximum way number Wmax of an interleave control is prepared and held, and utilization prohibition information is recorded in the area including the abnormal portion of the real address area utilization table when the abnormality of the memory element is detected.