Abstract: In a wafer polishing method, a within-wafer distribution model of a removal rate and a within-wafer distribution model of a polishing process are selected, and a within-wafer distribution of a removal rate is obtained by determining parameters of a within-wafer distribution model of a removal rate based on the within-wafer distribution of the film thickness before/after CMP, polishing condition data, and the selected within-wafer distribution model of the polishing process of the polished wafer. Then, a film thickness in the polishing process is estimated from passage of time based on the obtained within-wafer distribution of the removal rate, the selected within-wafer distribution model of the polishing process, and the film thickness before CMP of the wafer to be processed, thereby determining the polishing conditions with a restriction that the film thickness at each position in the within-wafer distribution of the film thickness after CMP satisfies the control limit.

Abstract: In a wafer polishing method, a within-wafer distribution model of a removal rate and a within-wafer distribution model of a polishing process are selected, and a within-wafer distribution of a removal rate is obtained by determining parameters of a within-wafer distribution model of a removal rate based on the within-wafer distribution of the film thickness before/after CMP, polishing condition data, and the selected within-wafer distribution model of the polishing process of the polished wafer. Then, a film thickness in the polishing process is estimated from passage of time based on the obtained within-wafer distribution of the removal rate, the selected within-wafer distribution model of the polishing process, and the film thickness before CMP of the wafer to be processed, thereby determining the polishing conditions with a restriction that the film thickness at each position in the within-wafer distribution of the film thickness after CMP satisfies the control limit.

Abstract: Disclosed is a method to achieve the planarization of a BPSG film and reduction of micro-scratches on a BPSG film by the CMP method. A BPSG film is deposited over a main surface of a substrate on which MISFETs have been formed, and then, a surface of the BPSG film is planarized by the CMP method. Thereafter, a thermal treatment is performed to the substrate to reflow the BPSG film, thereby removing the micro-scratches on the surface of the BPSG film caused by the polishing. At this time, the amount of polishing of the surface of the BPSG film is controlled within a range of 90 to 300 nm, preferably 100 to 250 nm, and more preferably 120 to 200 nm.