Abstract: A mode determination circuit is configured to determine whether there is a status change of the electric system associated with a frequency variation of a system control clock, and a clock change circuit is configured to change the system control clock from a system clock to a monitoring clock based on a determination result obtained by the mode determination circuit.

Abstract: A mode determination circuit is configured to determine whether there is a status change of the electric system associated with a frequency variation of a system control clock, and a clock change circuit is configured to change the system control clock from a system clock to a monitoring clock based on a determination result obtained by the mode determination circuit.

Abstract: In a tone output device 100, an oscillator 102 outputs a clock 141 that is emitted by a crystal resonator. A multiplication circuit 103 outputs a clock 142 that is generated by multiplying the clock 141. A timing control circuit 104 outputs a timing signal 150 generated based on the clock 142 for operations of a CPU 105. The CPU 105 operates in sync with the timing signal 150. The DA converter 115 operates in sync with a signal generated based on the clock 141. The timing adjustment circuit 114 detects deviation of the clock 142 from the clock 141 resulting from frequency jitter of the clock 142, and prevents occurrence of clock racing.

Abstract: In a tone output device 100, an oscillator 102 outputs a clock 141 that is emitted by a crystal resonator. A multiplication circuit 103 outputs a clock 142 that is generated by multiplying the clock 141. A timing control circuit 104 outputs a timing signal 150 generated based on the clock 142 for operations of a CPU 105. The CPU 105 operates in sync with the timing signal 150. The DA converter 115 operates in sync with a signal generated based on the clock 141. The timing adjustment circuit 114 detects deviation of the clock 142 from the clock 141 resulting from frequency jitter of the clock 142, and prevents occurrence of clock racing.

Abstract: A security circuit and a security cancellation method in which a code generation program 300 is input from the outside when the access security of internal resource data 360 for a semiconductor integrated circuit is to be cancelled, and in which the access security cannot be cancelled and access to the internal resource data 360 is not allowed unless matching between the input code 330 generated by operating the code generation program 300 and a security code 340 stored in advance in the semiconductor integrated circuit is confirmed. The program is not leaky in comparison with the conventional code. The security circuit and the security cancellation method can therefore have an improved security level.