Patents by Inventor Kosei Maemura

Kosei Maemura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8932866
    Abstract: As a result of collecting blood from pancreatic cancer patients, esophageal cancer patients, and stomach cancer patients, and conducting mass spectrometry on N-linked sugar chains in the plasmas, sugar chains whose abundances are significantly different from those of healthy subjects have been successfully identified from the blood samples of the cancer patients.
    Type: Grant
    Filed: April 6, 2011
    Date of Patent: January 13, 2015
    Assignees: Kagoshima University, Sumitomo Bakelite Co., Ltd.
    Inventors: Shoji Natsugoe, Yasuto Uchikado, Teruto Hashiguchi, Hiroyuki Shinchi, Kosei Maemura, Yuko Mataki, Norichika Moriwaki, Masaru Sekijima, Hideyuki Shimaoka, Midori Abe, Masao Fukushima, Kota Igarashi, Hiroki Abe, Taichi Aihara
  • Publication number: 20140273049
    Abstract: A diagnostic marker for digestive organ cancer according to the present invention is used for determining whether or not to have a digestive organ cancer. The diagnostic marker for digestive organ cancer contains at least one of N-binding type sugar chains released from a glycoprotein contained in blood and represented by the following formulas (1) to (6). This makes it possible to provide a diagnostic marker for digestive organ cancer capable of being used for an inspection method of easily determining whether or not to have a digestive organ cancer at an early stage, and an inspection method for digestive organ cancer of easily determining whether or not to have a digestive organ cancer at an early stage.
    Type: Application
    Filed: October 5, 2012
    Publication date: September 18, 2014
    Applicants: Kagoshima University, SUMITOMO BAKELITE COMPANY LIMITED
    Inventors: Shoji Natsugoe, Yasuto Uchikado, Teruto Hashiguchi, Hiroyuki Shinchi, Kosei Maemura, Yuko Mataki, Norichika Moriwaki, Masaru Sekijima, Hideyuki Shimaoka, Midori Sakaguchi, Masao Fukushima, Kota Igarashi, Hiroki Abe, Taichi Aihara
  • Publication number: 20130109043
    Abstract: As a result of collecting blood from pancreatic cancer patients, esophageal cancer patients, and stomach cancer patients, and conducting mass spectrometry on N-linked sugar chains in the plasmas, sugar chains whose abundances are significantly different from those of healthy subjects have been successfully identified from the blood samples of the cancer patients.
    Type: Application
    Filed: April 6, 2011
    Publication date: May 2, 2013
    Applicants: KAGOSHIMA UNIVERSITY, MITSUBISHI CHEMICAL MEDIENCE CORPORATION, SUMITOMO BAKELITE CO., LTD.
    Inventors: Shoji Natsugoe, Yasuto Uchikado, Teruto Hashiguchi, Hiroyuki Shinchi, Kosei Maemura, Yuko Mataki, Norichika Moriwaki, Masaru Sekijima, Hideyuki Shimaoka, Midori Abe, Masao Fukushima, Kota Igarashi, Hiroki Abe, Taichi Aihara
  • Patent number: 7554394
    Abstract: In a third operation in an amplifier, in which first and second amplifier circuits amplify a input signal, a distribution circuit adjusts the power of the signal supplied to the first amplifier circuit to within a range in which the input power to the first amplifier circuit and the output power from the first amplifier are proportional to each other. In a linear operation, the power of the signal from the first amplifier circuit and input to the comparison circuit and the power of the signal from the second amplifier circuit and input to the comparison circuit are equal. The comparison circuit adjusts the gain or the saturated power of the second amplifier circuit on the basis of the difference between the signals from the first and second amplifier circuits and input to the comparison circuit, so that the input power to the second amplifier circuit and the output power from the second amplifier circuit are proportional to each other.
    Type: Grant
    Filed: August 6, 2007
    Date of Patent: June 30, 2009
    Assignee: Mitsubishi Electric Corporation
    Inventor: Kosei Maemura
  • Publication number: 20080231358
    Abstract: In a third operation in an amplifier, in which first and second amplifier circuits amplify a input signal, a distribution circuit adjusts the power of the signal supplied to the first amplifier circuit to within a range in which the input power to the first amplifier circuit and the output power from the first amplifier are proportional to each other. In a linear operation, the power of the signal from the first amplifier circuit and input to the comparison circuit and the power of the signal from the second amplifier circuit and input to the comparison circuit are equal. The comparison circuit adjusts the gain or the saturated power of the second amplifier circuit on the basis of the difference between the signals from the first and second amplifier circuits and input to the comparison circuit, so that the input power to the second amplifier circuit and the output power from the second amplifier circuit are proportional to each other.
    Type: Application
    Filed: August 6, 2007
    Publication date: September 25, 2008
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventor: Kosei Maemura
  • Patent number: 7417507
    Abstract: A combined bias circuit in which a voltage drive bias circuit and a current drive bias circuit are provided in parallel with each other has a configuration in which a linearizer including a first resistor is connected between an amplifying transistor and a second resistor. This configuration ensures that even when a low voltage of 2.4 to 2.5 V is supplied as an external reference voltage, the amplifying operation can be performed while generally constantly maintaining an idling current in a temperature range from a low temperature to a high temperature, and that degradation in distortion characteristics during low-temperature operation can be limited.
    Type: Grant
    Filed: November 3, 2006
    Date of Patent: August 26, 2008
    Assignee: Mitsubishi Electric Corporation
    Inventors: Kazuya Yamamoto, Tomoyuki Asada, Hiroyuki Otsuka, Kosei Maemura
  • Publication number: 20070273447
    Abstract: A combined bias circuit in which a voltage drive bias circuit and a current drive bias circuit are provided in parallel with each other has a configuration in which a linearizer including a first resistor is connected between an amplifying transistor and a second resistor. This configuration ensures that even when a low voltage of 2.4 to 2.5 V is supplied as an external reference voltage, the amplifying operation can be performed while generally constantly maintaining an idling current in a temperature range from a low temperature to a high temperature, and that degradation in distortion characteristics during low-temperature operation can be limited.
    Type: Application
    Filed: November 3, 2006
    Publication date: November 29, 2007
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Kazuya YAMAMOTO, Tomoyuki ASADA, Hiroyuki OTSUKA, Kosei MAEMURA
  • Patent number: 6946913
    Abstract: A high-frequency amplifier has an amplifying transistor and a bias circuit that supplies a bias current to the base of the amplifier transistor. The bias circuit has a reference voltage input terminal to which a reference voltage is input from an external source, a first transistor that supplies a bias current to the base of the amplifier transistor in response to the reference voltage, a second transistor whose collector is connected to the connecting point of the first transistor to the base of the amplifying transistor, and whose emitter is grounded, a third transistor that supplies a bias current to the base of the second transistor in response to the reference voltage, and temperature compensation portions connected between the connecting point of the control input terminal to the third transistor and the grounding point.
    Type: Grant
    Filed: January 14, 2004
    Date of Patent: September 20, 2005
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Takao Moriwaki, Yuji Yamamoto, Kosei Maemura
  • Publication number: 20040251967
    Abstract: A high-frequency amplifier has an amplifying transistor and a bias circuit that supplies a bias current to the base of the amplifier transistor. The bias circuit has a reference voltage input terminal to which a reference voltage is input from an external source, a first transistor that supplies a bias current to the base of the amplifier transistor in response to the reference voltage, a second transistor whose collector is connected to the connecting point of the first transistor to the base of the amplifying transistor, and whose emitter is grounded, a third transistor that supplies a bias current to the base of the second transistor in response to the reference voltage, and temperature compensation portions connected between the connecting point of the control input terminal to the third transistor and the grounding point.
    Type: Application
    Filed: January 14, 2004
    Publication date: December 16, 2004
    Applicant: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Takao Moriwaki, Yuji Yamamoto, Kosei Maemura
  • Patent number: 6308047
    Abstract: In an RF front end portion for processing a radio-frequency signal in a portable telephone, a low pass filter allowing passing of only a signal in a frequency band lower than a radio-frequency signal component band is arranged between a circuit processing a high power signal and a control circuit controlling operation of the radio-frequency signal processing circuit. The radio-frequency signal processing circuit is a transmission/reception multiplexing circuit transferring a transmission signal of the portable telephone to an antenna or receiving a reception signal from the antenna, and the control circuit is a transmission/reception control circuit determining an operation mode of the transmission/reception multiplexing switch. Alternatively, the radio-frequency signal processing circuit includes a power amplifier amplifying a signal to be transmitted, and a gate voltage control circuit generating gate bias voltage controlling a gain of the power amplifier.
    Type: Grant
    Filed: February 3, 1999
    Date of Patent: October 23, 2001
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Kazuya Yamamoto, Kosei Maemura
  • Patent number: 5878331
    Abstract: An integrated circuit includes a single pole double throw switch including a transmitting and receiving port, a transmitting port, and a receiving port. A transmission switch is coupled between the transmitting port and the transmitting and receiving port. A reception switch is coupled between the receiving port and the transmitting and receiving port. The reception switch includes a field effect transistor having a gate, a drain and a source. A voltage generating circuit receives first and second power supply voltages. The first power supply voltage is greater than the second power supply voltage. The voltage generating circuit generates a third voltage lower than the second power supply voltage and applies the third voltage to the gate of the field effect transistor of the reception switch during transmission.
    Type: Grant
    Filed: July 30, 1996
    Date of Patent: March 2, 1999
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Kazuya Yamamoto, Kosei Maemura
  • Patent number: 5699018
    Abstract: An output voltage of a negative voltage generator contains a ripple because of a ripple occurring in a voltage produced by a charge pump circuit in the negative voltage generator. When the negative voltage is supplied to an FET amplifier, there arises a possibility that an unwanted spurious component occurs in an output of the FET amplifier. Since each of pair of circuits, that generate a negative voltage, are made mutually complementary, two charge pump circuits are used to cancel ripples. A ripple appearing in an output voltage can therefore be suppressed, and a negative voltage can eventually be supplied more stably. When the negative voltage generator is connected to, for example, an FET amplifier in order to supply a gate bias voltage to each FET in the FET amplifier, an unwanted spurious component that may be contained in an output of the FET amplifier can be removed.
    Type: Grant
    Filed: May 3, 1996
    Date of Patent: December 16, 1997
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Kazuya Yamamoto, Kosei Maemura
  • Patent number: 5548825
    Abstract: A transmitter of a radio communication apparatus includes a voltage controlled oscillator for converting a voltage signal input to the transmitter into a signal having a frequency according to the voltage of the voltage signal, a mixer for mixing a signal having a fixed frequency with the converted input signal and generating a signal for transmission having a frequency at which communication is substantially carried out, a frequency detector for detecting the frequency at which communication is substantially carried out, and a filter for eliminating useless signals that are included in the signal for transmission and have frequencies different from the frequency at which communication is substantially carried out. Signals having frequencies different from the frequency at which communication is substantially carried out are not radiated into space.
    Type: Grant
    Filed: June 30, 1994
    Date of Patent: August 20, 1996
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Kosei Maemura, Kazuya Yamamoto
  • Patent number: 5084907
    Abstract: A two-modulus variable frequency-divider circuit comprises a variable frequency-divider, a plurality of .div.2 frequency-dividers succeeding the variable frequency-divider, and a monitor. Outputs of one or more of the .div.2 frequency-dividers are coupled to the monitor which develops a monitor output determined by the states of the .div.2 frequency-divider outputs applied thereto. The monitor output is fed back to the variable frequency-divider as a frequency dividing factor setting signal. The two-modulus variable frequency-divider circuit is further provided with a signal converting circuit having a signal inverting function, which can selectively invert, in accordance with an externally applied control signal, the output of the two-modulus variable frequency-divider circuit or the output of the final one of those .div.2 frequency dividers which provide the outputs thereof to the monitor.
    Type: Grant
    Filed: November 21, 1989
    Date of Patent: January 28, 1992
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Kosei Maemura