Patents by Inventor Koshi HIMEDA

Koshi HIMEDA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240420899
    Abstract: An electronic component that includes: a sealing body having a first plate, a cover part spaced form the first plate, and a sealing metal layer; a functional part spaced from the first plate and in an airtight internal space of the sealing body; a filling resin part filling a space between the sealing body and the functional part; and a via conductor in a first through hole extending through the first plate and in a second through hole extending through the filling resin part and communicating with the first through hole, the via conductor being electrically connected to a pair of electrodes of the functional part. A water vapor transmission rate of the cover part is less than or equal to one-tenth of a water vapor transmission rate of the filling resin part having the same film thickness, or the cover part is made of glass or metal.
    Type: Application
    Filed: August 30, 2024
    Publication date: December 19, 2024
    Inventors: Tomoyuki ASHIMINE, Satoshi SHINDO, Koshi HIMEDA
  • Publication number: 20240379280
    Abstract: An inductor component includes an element body including a magnetic layer, a first coil and a second coil that are disposed adjacent to each other on a plane in the element body, and a first connection conductor that connects the first coil and the second coil. A first axis of the first coil and a second axis of the second coil are disposed parallel in a first direction that is orthogonal to the plane. A shortest distance between the first coil and the second coil is equal to or greater than a larger wiring width of a first wiring width of the first coil and a second wiring width of the second coil, and is equal to or less than an average value of a first diameter of a first smallest circle enclosing the first coil and a second diameter of a second smallest circle enclosing the second coil.
    Type: Application
    Filed: July 22, 2024
    Publication date: November 14, 2024
    Inventors: Nobuyoshi ADACHI, Koshi HIMEDA, Yoshimitsu USHIMI, Kenji NISHIYAMA
  • Publication number: 20240380324
    Abstract: A voltage converter is provided that includes a variable inductor device that is disposed between an input line and an output line, a switching device that is disposed between the input line and the variable inductor device, a capacitor that is disposed between the output line and a ground line and a control circuit configured to switch an inductance value of the variable inductor device and to switch a control mode of the switching device according to a load current in the output line. The control circuit is configured to set the inductance value of the variable inductor device to a first value when the load current is less than a threshold value and set the inductance value of the variable inductor device to a second value that is smaller than the first value when the load current is higher than the threshold value.
    Type: Application
    Filed: July 22, 2024
    Publication date: November 14, 2024
    Inventors: Yoshimitsu USHIMI, Koshi HIMEDA, Nobuyoshi ADACHI, Kenji NISHIYAMA
  • Publication number: 20240355537
    Abstract: An inductor component includes an element body having a magnetic material, and a coil that is disposed inside the element body. The coil includes a coil wire that is spirally wound along an axis with a first end of the coil wire at a positive side of the axis and a second end of the coil wire at a negative side of the axis. At least one of a first end surface of the first end of the coil wire and a second end surface of the second end of the coil wire includes a recess, and a portion of the element body is located inside the recess.
    Type: Application
    Filed: June 28, 2024
    Publication date: October 24, 2024
    Inventors: Yoshimitsu USHIMI, Koshi HIMEDA, Kenji NISHIYAMA, Hidehiko SASAKI, Nobuyoshi ADACHI
  • Publication number: 20240355532
    Abstract: A coil that includes a coil wire spirally wound along an axis. The coil wire includes a first wiring portion and a second wiring portion which are aligned along the axis. The first wiring portion includes a first end surface on a side in a first direction from the first wiring portion toward the second wiring portion, and a second end surface on a side in a second direction opposite to the first direction. The first end surface includes a first end in an inner side portion in a radial direction of the coil wire. The second end surface is in an outer side portion in the radial direction of the coil wire with respect to a straight line passing through the first end and parallel to the direction of the axis.
    Type: Application
    Filed: July 2, 2024
    Publication date: October 24, 2024
    Inventors: Yoshimitsu USHIMI, Koshi Himeda, Kenji Nishiyama, Hidehiko Sasaki, Nobuyoshi Adachi
  • Publication number: 20240355527
    Abstract: A package substrate that includes: an inductor layer having a magnetic body and inductor wires. The magnetic body includes a first magnetic layer and a second magnetic layer on at least one main surface of the first magnetic layer. The inductor wires are in the first magnetic layer and include a first wire and a second wire adjacent to each other and magnetically coupled. The second magnetic layer overlaps the first wire and the second wire in a thickness direction. The second magnetic layer has anisotropic magnetic permeability in which magnetic permeability in a main surface direction differs from the thickness direction. The magnetic permeability of the second magnetic layer in the main surface direction is higher than in the thickness direction. The magnetic permeability of the second magnetic layer in the main surface direction is higher than magnetic permeability of the first magnetic layer in a main surface direction.
    Type: Application
    Filed: July 2, 2024
    Publication date: October 24, 2024
    Inventors: Kenji NISHIYAMA, Yoshimitsu USHIMI, Koshi HIMEDA, Nobuyoshi ADACHI
  • Publication number: 20240355533
    Abstract: A coil that includes: a coil wire spirally wound along an axis; and an insulator that covers at least a portion of the coil wire. In a cross section including the axis, the insulator includes: a first insulation portion in contact with a first end surface of the coil wire on a first side in a direction of the axis of the coil wire, a second insulation portion in contact with a second end surface of the coil wire on a second side in the direction of the axis of the coil wire, and a third insulation portion between adjacent turns in the direction of the axis of the coil wire. At least one of a first thickness of the first insulation portion and a second thickness of the second insulation portion is thinner than half of a third thickness of the third insulation portion.
    Type: Application
    Filed: July 2, 2024
    Publication date: October 24, 2024
    Inventors: Yoshimitsu USHIMI, Koshi HIMEDA, Kenji NISHIYAMA, Hidehiko SASAKI, Nobuyoshi ADACHI
  • Publication number: 20240242892
    Abstract: A capacitor element that includes: a capacitor portion including an anode plate having a porous portion on a core portion, a dielectric layer on the porous portion, and a cathode layer on the dielectric layer; a first cathode through conductor and a second cathode through conductor each penetrating the dielectric layer and the anode plate in a thickness direction and electrically connected to the cathode layer; and an anode through conductor penetrating the dielectric layer and the anode plate in the thickness direction and electrically connected to the anode plate, wherein, in a plan view from a thickness direction of the anode plate, a first center-to-center distance between the first anode through conductor and the first cathode through conductor is equivalent to a second center-to-center distance between the first anode through conductor and the second cathode through conductor.
    Type: Application
    Filed: March 27, 2024
    Publication date: July 18, 2024
    Inventors: Akitomo TAKAHASHI, Takeshi FURUKAWA, Koshi HIMEDA
  • Patent number: 12009273
    Abstract: A semiconductor apparatus includes a substrate, plural transistor groups disposed on the substrate, an insulating film, and a metal member. Each of the plural transistor groups includes plural unit transistors arranged in a first direction within a plane of a top surface of the substrate. The plural transistor groups are arranged in a second direction perpendicular to the first direction. The insulating film covers the plural unit transistors and includes at least one cavity. The metal member is disposed on the insulating film and is electrically connected to the plural unit transistors via the at least one cavity. A heat transfer path is formed by a metal in a region from each of the plural unit transistors to a top surface of the metal member. Thermal resistance values of the heat transfer paths are different from each other among the plural unit transistors.
    Type: Grant
    Filed: January 22, 2020
    Date of Patent: June 11, 2024
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Atsushi Kurokawa, Koshi Himeda, Kazuya Kobayashi
  • Patent number: 11863128
    Abstract: A power amplifier circuit includes a first transistor disposed on a semiconductor substrate; a second transistor that supplies a bias current based on a first current which is a part of a control current to the first transistor; a current output element in which a current flowing therethrough increases in accordance with a rise in temperature; and a wiring portion including a plurality of metal layers that are electrically connected to an emitter of the first transistor and that are stacked one on top of another so as to oppose the semiconductor substrate. At least one metal layer among the plurality of metal layers extends so as to overlap an area extending from at least a part of a first disposition area in which the first transistor is disposed to a second disposition area in which the current output element is disposed in plan view of the semiconductor substrate.
    Type: Grant
    Filed: February 4, 2021
    Date of Patent: January 2, 2024
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Hideyuki Sato, Koshi Himeda
  • Patent number: 11817493
    Abstract: A semiconductor device includes a substrate having an upper surface on which are arranged first transistors each including a mesa structure formed of a semiconductor. A first bump having a shape elongated in one direction in plan view and connected to the first transistors is arranged at a position overlapping the first transistors in plan view. A second bump has a space with respect to the first bump in a direction orthogonal to a longitudinal direction of the first bump. A first metal pattern is arranged between the first and second bumps in plan view. When the upper surface of the substrate is taken as a height reference, a center of the first metal pattern in a thickness direction has a height higher than an upper surface of the mesa structure included in each of the first transistors and lower than a lower surface of the first bump.
    Type: Grant
    Filed: December 8, 2021
    Date of Patent: November 14, 2023
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Mari Saji, Atsushi Kurokawa, Koshi Himeda
  • Publication number: 20230109290
    Abstract: A semiconductor composite device includes active elements and passive elements constituting a voltage regulator and disposed in association with a plurality of channels, a load to be supplied with a direct-current voltage regulated by the voltage regulator, and a wiring board electrically connected to the active elements, the passive elements, and the load. A plurality of capacitors disposed in the channels include an integrally formed capacitor array including a plurality of capacitor portions disposed in a plane. The capacitor array includes a plurality of through hole conductors extending through the capacitor array in a direction perpendicular to a mounting surface of the wiring board. At least a part of the capacitor array is positioned to overlap the load when viewed from the mounting surface of the wiring board.
    Type: Application
    Filed: December 12, 2022
    Publication date: April 6, 2023
    Inventors: Tatsuya KITAMURA, Koshi HIMEDA, Takeshi FURUKAWA
  • Patent number: 11552020
    Abstract: A semiconductor composite device is provided that includes a voltage regulator, a package board, and a load, and converts an input DC voltage into a different DC voltage to supply the converted DC voltage to the load. The VR includes a semiconductor active element. The package board includes a C layer in which a capacitor is formed, and an L layer in which an inductor is formed. A plurality of through holes penetrate the C layer and the L layer in a direction perpendicular to the mounting face in the package board. The capacitor is connected to the load through the through hole. The inductor is connected to the load through the through hole and to the VR through the through hole.
    Type: Grant
    Filed: August 10, 2021
    Date of Patent: January 10, 2023
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Koshi Himeda, Tatsuya Kitamura, Chiharu Sakaki, Shinya Kiyono, Sho Fujita, Atsushi Yamamoto, Takeshi Furukawa, Kenji Nishiyama, Tatsuya Funaki, Kinya Aoki
  • Patent number: 11515442
    Abstract: An optical semiconductor element having a mesa portion includes a substrate and semiconductor layers on the substrate. The optical semiconductor element further includes a first contact electrode, a second contact electrode on the semiconductor layer, first and second lead-out wires connected to the first and second contact electrodes, respectively, and an insulating film covering at least an upper surface of the semiconductor layer and the second contact electrode. The second lead-out wire is connected to the second contact electrode in an opening of the insulating film. An outer peripheral end of the second contact electrode in at least a portion where the second contact electrode and the second lead-out wire are connected is above and outside an outer peripheral end of a connection portion with the semiconductor layer, and an inner peripheral end is above and inside an inner peripheral end of the connection portion with the semiconductor layer.
    Type: Grant
    Filed: October 2, 2020
    Date of Patent: November 29, 2022
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Kenji Fujimoto, Koshi Himeda, Toshihiro Tada, Tetsuro Toritsuka, Shinji Kaburaki
  • Publication number: 20220336381
    Abstract: A package board that includes an inductor layer having: a first magnetic layer including first magnetic particles and a resin; an inductor wiring that functions as an inductor in the first magnetic layer; and a second magnetic layer on at least one surface of the first magnetic layer, including second magnetic particles that are higher in average flatness than the first magnetic particles and a resin, the second magnetic particles having a shape where the dimension in a direction along the main surface of the second magnetic layer is longer than the dimension in the thickness direction of the second magnetic layer.
    Type: Application
    Filed: April 12, 2022
    Publication date: October 20, 2022
    Inventors: Kenji NISHIYAMA, Koshi HIMEDA, Yoshimitsu USHIMI
  • Patent number: 11437182
    Abstract: An electronic component comprising a coil component having an element body containing ceramic, a coil disposed in the element body, and an external electrode disposed in the element body and electrically connected to the coil; and a mold resin sealing the coil component. The electronic component further comprises an electrode film in contact with an outer surface of the mold resin; and a connection conductor disposed in the mold resin and electrically connecting the external electrode and the electrode film.
    Type: Grant
    Filed: October 30, 2018
    Date of Patent: September 6, 2022
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Koichi Yamaguchi, Koshi Himeda
  • Patent number: 11398341
    Abstract: An electronic component comprising a main body part including an insulating layer and a conductor layer laminated alternately. The insulating layer and the conductor layer are partially exposed on a side surface of the main body part in a direction orthogonal to a lamination direction. Also, the side surface of the main body part is provided with a metal film extending in the lamination direction to cover the insulating layer and the conductor layer exposed on the side surface.
    Type: Grant
    Filed: October 25, 2018
    Date of Patent: July 26, 2022
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Yoshinori Ueda, Koshi Himeda, Hayami Kudo
  • Publication number: 20220200551
    Abstract: A power amplification device includes a first member in which a first circuit is formed, a second member in which a second circuit is formed, and a member-member connection conductor that electrically connects the first circuit and the second circuit to each other. The second member is mounted on the first member. The second circuit includes a first amplifier, which amplifies a radio frequency signal to output a first amplified signal. The first circuit includes a control circuit that controls an operation of the second circuit. At least part of a first termination circuit, which is connected to the first amplifier through the member-member connection conductor and which attenuates a harmonic wave component of the first amplified signal, is formed in the first member.
    Type: Application
    Filed: December 13, 2021
    Publication date: June 23, 2022
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Mitsunori SAMATA, Satoshi ARAYASHIKI, Koshi HIMEDA, Masayuki AOIKE
  • Publication number: 20220181470
    Abstract: A semiconductor device includes a substrate having an upper surface on which are arranged first transistors each including a mesa structure formed of a semiconductor. A first bump having a shape elongated in one direction in plan view and connected to the first transistors is arranged at a position overlapping the first transistors in plan view. A second bump has a space with respect to the first bump in a direction orthogonal to a longitudinal direction of the first bump. A first metal pattern is arranged between the first and second bumps in plan view. When the upper surface of the substrate is taken as a height reference, a center of the first metal pattern in a thickness direction has a height higher than an upper surface of the mesa structure included in each of the first transistors and lower than a lower surface of the first bump.
    Type: Application
    Filed: December 8, 2021
    Publication date: June 9, 2022
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Mari SAJI, Atsushi KUROKAWA, Koshi HIMEDA
  • Publication number: 20220157930
    Abstract: A passive component includes a substrate having insulating properties and having a surface having a recess, a bottom electrode filling at least a portion of the recess, a dielectric film provided on a surface of the bottom electrode, and a top electrode opposite to the bottom electrode with the dielectric film interposed therebetween. In a height direction perpendicular to the surface of the substrate, a dimension of the bottom electrode is larger than a dimension of the dielectric film.
    Type: Application
    Filed: November 15, 2021
    Publication date: May 19, 2022
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Hisaki KITAGAWA, Koshi HIMEDA, Jyou KIKURA