Patents by Inventor Koshi HIMEDA

Koshi HIMEDA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11437182
    Abstract: An electronic component comprising a coil component having an element body containing ceramic, a coil disposed in the element body, and an external electrode disposed in the element body and electrically connected to the coil; and a mold resin sealing the coil component. The electronic component further comprises an electrode film in contact with an outer surface of the mold resin; and a connection conductor disposed in the mold resin and electrically connecting the external electrode and the electrode film.
    Type: Grant
    Filed: October 30, 2018
    Date of Patent: September 6, 2022
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Koichi Yamaguchi, Koshi Himeda
  • Patent number: 11398341
    Abstract: An electronic component comprising a main body part including an insulating layer and a conductor layer laminated alternately. The insulating layer and the conductor layer are partially exposed on a side surface of the main body part in a direction orthogonal to a lamination direction. Also, the side surface of the main body part is provided with a metal film extending in the lamination direction to cover the insulating layer and the conductor layer exposed on the side surface.
    Type: Grant
    Filed: October 25, 2018
    Date of Patent: July 26, 2022
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Yoshinori Ueda, Koshi Himeda, Hayami Kudo
  • Publication number: 20220200551
    Abstract: A power amplification device includes a first member in which a first circuit is formed, a second member in which a second circuit is formed, and a member-member connection conductor that electrically connects the first circuit and the second circuit to each other. The second member is mounted on the first member. The second circuit includes a first amplifier, which amplifies a radio frequency signal to output a first amplified signal. The first circuit includes a control circuit that controls an operation of the second circuit. At least part of a first termination circuit, which is connected to the first amplifier through the member-member connection conductor and which attenuates a harmonic wave component of the first amplified signal, is formed in the first member.
    Type: Application
    Filed: December 13, 2021
    Publication date: June 23, 2022
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Mitsunori SAMATA, Satoshi ARAYASHIKI, Koshi HIMEDA, Masayuki AOIKE
  • Publication number: 20220181470
    Abstract: A semiconductor device includes a substrate having an upper surface on which are arranged first transistors each including a mesa structure formed of a semiconductor. A first bump having a shape elongated in one direction in plan view and connected to the first transistors is arranged at a position overlapping the first transistors in plan view. A second bump has a space with respect to the first bump in a direction orthogonal to a longitudinal direction of the first bump. A first metal pattern is arranged between the first and second bumps in plan view. When the upper surface of the substrate is taken as a height reference, a center of the first metal pattern in a thickness direction has a height higher than an upper surface of the mesa structure included in each of the first transistors and lower than a lower surface of the first bump.
    Type: Application
    Filed: December 8, 2021
    Publication date: June 9, 2022
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Mari SAJI, Atsushi KUROKAWA, Koshi HIMEDA
  • Publication number: 20220157930
    Abstract: A passive component includes a substrate having insulating properties and having a surface having a recess, a bottom electrode filling at least a portion of the recess, a dielectric film provided on a surface of the bottom electrode, and a top electrode opposite to the bottom electrode with the dielectric film interposed therebetween. In a height direction perpendicular to the surface of the substrate, a dimension of the bottom electrode is larger than a dimension of the dielectric film.
    Type: Application
    Filed: November 15, 2021
    Publication date: May 19, 2022
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Hisaki KITAGAWA, Koshi HIMEDA, Jyou KIKURA
  • Publication number: 20220157748
    Abstract: A mounting substrate has one main surface (a first main surface). An electronic component has a first face, a second face, and a side face, and is provided on the one main surface of the mounting substrate. A solder bump is disposed between the mounting substrate and the electronic component, and electrically connects the mounting substrate and the electronic component. A resin layer is provided on the one main surface of the mounting substrate to cover the electronic component. The first face is a face of the electronic component at a side opposite to the mounting substrate. The side face of the electronic component is in contact with the resin layer. A space is provided between at least a part of the first face and the resin layer in a thickness direction of the mounting substrate.
    Type: Application
    Filed: January 28, 2022
    Publication date: May 19, 2022
    Inventors: Mayuka ONO, Motoji TSUDA, Fumio HARIMA, Koshi HIMEDA, Hiroaki TOKUYA
  • Publication number: 20210375841
    Abstract: A semiconductor composite device is provided that includes a voltage regulator, a package board, and a load, and converts an input DC voltage into a different DC voltage to supply the converted DC voltage to the load. The VR includes a semiconductor active element. The package board includes a C layer in which a capacitor is formed, and an L layer in which an inductor is formed. A plurality of through holes penetrate the C layer and the L layer in a direction perpendicular to the mounting face in the package board. The capacitor is connected to the load through the through hole. The inductor is connected to the load through the through hole and to the VR through the through hole.
    Type: Application
    Filed: August 10, 2021
    Publication date: December 2, 2021
    Inventors: Koshi Himeda, Tatsuya Kitamura, Chiharu Sakaki, Shinya Kiyono, Sho Fujita, Atsushi Yamamoto, Takeshi Furukawa, Kenji Nishiyama, Tatsuya Funaki, Kinya Aoki
  • Patent number: 11145607
    Abstract: A semiconductor chip includes a compound semiconductor substrate having a pair of main surfaces and a side surface therebetween, a circuit on one main surface of the pair of main surfaces, and first metals on the main surface. The first metals are positioned, in plan view of the main surface, closer to an outer edge of the main surface than the circuit, substantially in a ring shape to surround the circuit with gaps between first metals adjacent to each other. The semiconductor chip further includes second metals on the main surface. The second metals are positioned, in plan view of the main surface, between the circuit and the first metals or closer to the outer edge than the first metals. Also, the second metals each are positioned, in plan view of the side surface, such that at least a part thereof overlaps a gap between the first metals.
    Type: Grant
    Filed: April 2, 2020
    Date of Patent: October 12, 2021
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Yusuke Tanaka, Fumio Harima, Masayuki Aoike, Koshi Himeda
  • Patent number: 11121123
    Abstract: A semiconductor composite device is provided that includes a voltage regulator, a package board, and a load, and converts an input DC voltage into a different DC voltage to supply the converted DC voltage to the load. The VR includes a semiconductor active element. The package board includes a C layer in which a capacitor is formed, and an L layer in which an inductor is formed. A plurality of through holes penetrate the C layer and the L layer in a direction perpendicular to the mounting face in the package board. The capacitor is connected to the load through the through hole. The inductor is connected to the load through the through hole and to the VR through the through hole.
    Type: Grant
    Filed: June 22, 2020
    Date of Patent: September 14, 2021
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Koshi Himeda, Tatsuya Kitamura, Chiharu Sakaki, Shinya Kiyono, Sho Fujita, Atsushi Yamamoto, Takeshi Furukawa, Kenji Nishiyama, Tatsuya Funaki, Kinya Aoki
  • Publication number: 20210242836
    Abstract: A power amplifier circuit includes a first transistor disposed on a semiconductor substrate; a second transistor that supplies a bias current based on a first current which is a part of a control current to the first transistor; a current output element in which a current flowing therethrough increases in accordance with a rise in temperature; and a wiring portion including a plurality of metal layers that are electrically connected to an emitter of the first transistor and that are stacked one on top of another so as to oppose the semiconductor substrate. At least one metal layer among the plurality of metal layers extends so as to overlap an area extending from at least a part of a first disposition area in which the first transistor is disposed to a second disposition area in which the current output element is disposed in plan view of the semiconductor substrate.
    Type: Application
    Filed: February 4, 2021
    Publication date: August 5, 2021
    Inventors: Hideyuki SATO, Koshi HIMEDA
  • Publication number: 20210036176
    Abstract: An optical semiconductor element having a mesa portion includes a substrate and semiconductor layers on the substrate. The optical semiconductor element further includes a first contact electrode, a second contact electrode on the semiconductor layer, first and second lead-out wires connected to the first and second contact electrodes, respectively, and an insulating film covering at least an upper surface of the semiconductor layer and the second contact electrode. The second lead-out wire is connected to the second contact electrode in an opening of the insulating film. An outer peripheral end of the second contact electrode in at least a portion where the second contact electrode and the second lead-out wire are connected is above and outside an outer peripheral end of a connection portion with the semiconductor layer, and an inner peripheral end is above and inside an inner peripheral end of the connection portion with the semiconductor layer.
    Type: Application
    Filed: October 2, 2020
    Publication date: February 4, 2021
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Kenji FUJIMOTO, Koshi HIMEDA, Toshihiro TADA, Tetsuro TORITSUKA, Shinji KABURAKI
  • Publication number: 20200321323
    Abstract: A semiconductor composite device is provided that includes a voltage regulator, a package board, and a load, and converts an input DC voltage into a different DC voltage to supply the converted DC voltage to the load. The VR includes a semiconductor active element. The package board includes a C layer in which a capacitor is formed, and an L layer in which an inductor is formed. A plurality of through holes penetrate the C layer and the L layer in a direction perpendicular to the mounting face in the package board. The capacitor is connected to the load through the through hole. The inductor is connected to the load through the through hole and to the VR through the through hole.
    Type: Application
    Filed: June 22, 2020
    Publication date: October 8, 2020
    Inventors: Koshi Himeda, Tatsuya Kitamura, Chiharu Sakaki, Shinya Kiyono, Sho Fujita, Atsushi Yamamoto, Takeshi Furukawa, Kenji Nishiyama, Tatsuya Funaki, Kinya Aoki
  • Publication number: 20200321289
    Abstract: A semiconductor chip includes a compound semiconductor substrate having a pair of main surfaces and a side surface therebetween, a circuit on one main surface of the pair of main surfaces, and first metals on the main surface. The first metals are positioned, in plan view of the main surface, closer to an outer edge of the main surface than the circuit, substantially in a ring shape to surround the circuit with gaps between first metals adjacent to each other. The semiconductor chip further includes second metals on the main surface. The second metals are positioned, in plan view of the main surface, between the circuit and the first metals or closer to the outer edge than the first metals. Also, the second metals each are positioned, in plan view of the side surface, such that at least a part thereof overlaps a gap between the first metals.
    Type: Application
    Filed: April 2, 2020
    Publication date: October 8, 2020
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Yusuke TANAKA, Fumio HARIMA, Masayuki AOIKE, Koshi HIMEDA
  • Patent number: 10777667
    Abstract: A semiconductor device has bipolar transistors on a substrate. There is also an insulating film on the substrate, covering the bipolar transistors. On this insulating film is emitter wiring, sticking through openings in the insulating film (first openings) to be electrically coupled to the emitter layer of the bipolar transistors. On the emitter wiring is a protective film. On the protective film is a bump, sticking through an opening in the protective film (second opening) to be electrically coupled to the emitter wiring. In plan view, the second opening is included in the area that is inside the bump and outside the first openings.
    Type: Grant
    Filed: November 12, 2019
    Date of Patent: September 15, 2020
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Atsushi Kurokawa, Koshi Himeda, Kazuya Kobayashi
  • Publication number: 20200235026
    Abstract: A semiconductor apparatus includes a substrate, plural transistor groups disposed on the substrate, an insulating film, and a metal member. Each of the plural transistor groups includes plural unit transistors arranged in a first direction within a plane of a top surface of the substrate. The plural transistor groups are arranged in a second direction perpendicular to the first direction. The insulating film covers the plural unit transistors and includes at least one cavity. The metal member is disposed on the insulating film and is electrically connected to the plural unit transistors via the at least one cavity. A heat transfer path is formed by a metal in a region from each of the plural unit transistors to a top surface of the metal member. Thermal resistance values of the heat transfer paths are different from each other among the plural unit transistors.
    Type: Application
    Filed: January 22, 2020
    Publication date: July 23, 2020
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Atsushi KUROKAWA, Koshi HIMEDA, Kazuya KOBAYASHI
  • Publication number: 20200168725
    Abstract: A semiconductor device has bipolar transistors on a substrate. There is also an insulating film on the substrate, covering the bipolar transistors. On this insulating film is emitter wiring, sticking through openings in the insulating film (first openings) to be electrically coupled to the emitter layer of the bipolar transistors. On the emitter wiring is a protective film. On the protective film is a bump, sticking through an opening in the protective film (second opening) to be electrically coupled to the emitter wiring. In plan view, the second opening is included in the area that is inside the bump and outside the first openings.
    Type: Application
    Filed: November 12, 2019
    Publication date: May 28, 2020
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Atsushi KUROKAWA, Koshi HIMEDA, Kazuya KOBAYASHI
  • Publication number: 20190156991
    Abstract: An electronic component comprising a coil component having an element body containing ceramic, a coil disposed in the element body, and an external electrode disposed in the element body and electrically connected to the coil; and a mold resin sealing the coil component. The electronic component further comprises an electrode film in contact with an outer surface of the mold resin; and a connection conductor disposed in the mold resin and electrically connecting the external electrode and the electrode film.
    Type: Application
    Filed: October 30, 2018
    Publication date: May 23, 2019
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Koichi YAMAGUCHI, Koshi HIMEDA
  • Publication number: 20190066908
    Abstract: An electronic component comprising a main body part including an insulating layer and a conductor layer laminated alternately. The insulating layer and the conductor layer are partially exposed on a side surface of the main body part in a direction orthogonal to a lamination direction. Also, the side surface of the main body part is provided with a metal film extending in the lamination direction to cover the insulating layer and the conductor layer exposed on the side surface.
    Type: Application
    Filed: October 25, 2018
    Publication date: February 28, 2019
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Yoshinori UEDA, Koshi HIMEDA, Hayami KUDO
  • Patent number: 8933497
    Abstract: A semiconductor switch device and a method of manufacturing the semiconductor switch device are provided. The semiconductor switch device includes semiconductor elements on a single semiconductor substrate. At least one of the semiconductor elements constitutes a switch circuit and at least one other of the semiconductor elements constitutes a logic (connection) circuit. Each semiconductor element includes a recess, a gate electrode in the recess, a drain electrode, and a source electrode. In one representative aspect, the gate electrode in the switch circuit can have a rectangular external shape in section, and the gate electrode in the connection circuit has a shape in section other than rectangular.
    Type: Grant
    Filed: November 15, 2011
    Date of Patent: January 13, 2015
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Tsunekazu Saimei, Kazuya Kobayashi, Koshi Himeda, Nobuyoshi Okuda
  • Publication number: 20120091513
    Abstract: A semiconductor switch device and a method of manufacturing the semiconductor switch device are provided. The semiconductor switch device includes semiconductor elements on a single semiconductor substrate. At least one of the semiconductor elements constitutes a switch circuit and at least one other of the semiconductor elements constitutes a logic (connection) circuit. Each semiconductor element includes a recess, a gate electrode in the recess, a drain electrode, and a source electrode. In one representative aspect, the gate electrode in the switch circuit can have a rectangular external shape in section, and the gate electrode in the connection circuit has a shape in section other than rectangular.
    Type: Application
    Filed: November 15, 2011
    Publication date: April 19, 2012
    Applicant: MURATA MANUFACTURING CO., LTD.
    Inventors: Tsunekazu SAIMEI, Kazuya KOBAYASHI, Koshi HIMEDA, Nobuyoshi OKUDA