Abstract: A vibration welding device includes a base plate, a vibrating body, and a plurality of position adjusting jigs. The vibrating body is capable of vibrating while holding an interior part which is an object to be welded. The base plate is disposed below the vibrating body. The base plate holds an instrument panel which is an object to be welded. The position adjusting jigs are connected to the vibrating body so as to be adjustable in position. The plurality of position adjusting jigs are disposed independently of each other.

Abstract: A vibration welding device includes a base plate, a vibrating body, and a plurality of position adjusting jigs. The vibrating body is capable of vibrating while holding an interior part which is an object to be welded. The base plate is disposed below the vibrating body. The base plate holds an instrument panel which is an object to be welded. The position adjusting jigs are connected to the vibrating body so as to be adjustable in position. The plurality of position adjusting jigs are disposed independently of each other.

Abstract: A semiconductor device capable of reconfiguration, including: a plurality of logic units which configure an array and are connected to each other, wherein each logic unit includes a pair of a first and a second memory cell units, each of the first and the second memory cell units operates as a logic element when truth value table data is written in, which is configured so that a logic calculation of an input value specified by a plurality of addresses is output to a data line, and/or operates as a connection element when truth value table data is written in, which is configured so that an input value specified by a certain address is output to a data line to be connected to an address of another memory cell unit, a latter stage of the first memory cell unit includes a sequential circuit which synchronizes with a clock, and the logic units include, for each pair of the first and the second memory cell units, a selection unit which selectively outputs an address to the first or the second memory cell unit in ac

Abstract: A reconfigurable semiconductor device includes a plurality of logic units connected to each other via address lines or data lines, each of the logic units including: a plurality of address lines; a plurality of data lines; a first address decoder that decodes addresses inputted from some of the address lines; a second address decoder that decodes addresses inputted from the other of the address lines; a first memory cell unit having a plurality of memory cells and selecting, among said plurality of memory cells, a predetermined number of memory cells in accordance with the address decoded by the first address decoder; and a second memory cell unit having a plurality of memory cells and selecting, among said plurality of memory cells, a predetermined number of memory cells in accordance with the address decoded by the second address decoder.

Abstract: A semiconductor device capable of reconfiguration, including: a plurality of logic units which configure an array and are connected to each other, wherein each logic unit includes a pair of a first and a second memory cell units, each of the first and the second memory cell units operates as a logic element when truth value table data is written in, which is configured so that a logic calculation of an input value specified by a plurality of addresses is output to a data line, and/or operates as a connection element when truth value table data is written in, which is configured so that an input value specified by a certain address is output to a data line to be connected to an address of another memory cell unit, a latter stage of the first memory cell unit includes a sequential circuit which synchronizes with a clock, and the logic units include, for each pair of the first and the second memory cell units, a selection unit which selectively outputs an address to the first or the second memory cell unit in ac

Abstract: A reconfigurable semiconductor device includes a plurality of logic units connected to each other via address lines or data lines, each of the logic units including: a plurality of address lines; a plurality of data lines; a first address decoder that decodes addresses inputted from some of the address lines; a second address decoder that decodes addresses inputted from the other of the address lines; a first memory cell unit having a plurality of memory cells and selecting, among said plurality of memory cells, a predetermined number of memory cells in accordance with the address decoded by the first address decoder; and a second memory cell unit having a plurality of memory cells and selecting, among said plurality of memory cells, a predetermined number of memory cells in accordance with the address decoded by the second address decoder.

Abstract: A semiconductor device capable of reconfiguration, including: a plurality of logic units which configure an array and are connected to each other, wherein each logic unit includes a pair of a first and a second memory cell units, each of the first and the second memory cell units operates as a logic element when truth value table data is written in, which is configured so that a logic calculation of an input value specified by a plurality of addresses is output to a data line, and/or operates as a connection element when truth value table data is written in, which is configured so that an input value specified by a certain address is output to a data line to be connected to an address of another memory cell unit, a latter stage of the first memory cell unit includes a sequential circuit which synchronizes with a clock, and the logic units include, for each pair of the first and the second memory cell units, a selection unit which selectively outputs an address to the first or the second memory cell unit in ac

Abstract: A semiconductor device capable of reconfiguration, including: a plurality of logic units which configure an array and are connected to each other, wherein each logic unit includes a pair of a first and a second memory cell units, each of the first and the second memory cell units operates as a logic element when truth value table data is written in, which is configured so that a logic calculation of an input value specified by a plurality of addresses is output to a data line, and/or operates as a connection element when truth value table data is written in, which is configured so that an input value specified by a certain address is output to a data line to be connected to an address of another memory cell unit, a latter stage of the first memory cell unit includes a sequential circuit which synchronizes with a clock, and the logic units include, for each pair of the first and the second memory cell units, a selection unit which selectively outputs an address to the first or the second memory cell unit in ac

Abstract: To provide a toner, which contains a binder resin, a colorant, and a releasing agent, wherein the binder resin contains a low molecular weight resin component, where the low molecular weight resin component has a resin softening coefficient (A), represented by the following formula (1), satisfying A>0.165, and has storage elastic modulus (dyne/cm2) G?(Tfb) satisfying G?(Tfb)?1×104 where Tfb is a flow onset temperature (° C.) of the low molecular weight resin component as measured by a capillary rheometer: A=|[(r1)?ln G?(r2)]/(T1?T2)|??Formula (1) (where T1 is temperature (° C.) at which storage elastic modulus G?(r1) is 1×105 (dyne/cm2) and T2 is temperature (° C.) at which storage elastic modulus G?(r2) is 1×103 (dyne/cm2) as measured by means of a viscoelasticity measuring device with measuring frequency of 1 Hz, and measuring distortion of 1 deg; and | | represents an absolute value.).

Abstract: To provide a toner, which contains a binder resin, a colorant, and a releasing agent, wherein the binder resin contains a low molecular weight resin component, where the low molecular weight resin component has a resin softening coefficient (A), represented by the following formula (1), satisfying A>0.165, and has storage elastic modulus (dyne/cm2) G?(Tfb) satisfying G?(Tfb)?1×104 where Tfb is a flow onset temperature (° C.) of the low molecular weight resin component as measured by a capillary rheometer: A=|[ln G?(r1)?ln G?(r2)]/(T1?T2)|??Formula (1) (where T1 is temperature (° C.) at which storage elastic modulus G?(r1) is 1×105 (dyne/cm2) and T2 is temperature (° C.) at which storage elastic modulus G?(r2) is 1×103 (dyne/cm2) as measured by means of a viscoelasticity measuring device with measuring frequency of 1 Hz, and measuring distortion of 1 deg; and ? represents an absolute value.

Abstract: A toner which contains: toner base particles having Dv of 4.0-6.0 ?m; and two or more additives on surfaces of the toner base particles, where the additives contains Additives A and B, wherein the toner base particles are obtained by the method containing: dispersing, in an aqueous medium, an oil phase in which at least one of a crystalline polyester resin and a non-crystalline polyester resin is contained in an organic solvent, to prepare a dispersion liquid; and removing the organic solvent from the dispersion liquid, and wherein the Additive A has the largest average primary particle diameter in the additives and has CA of 5-10% where the CA is determined by the formula A, and the Additive B has the smallest average primary particle diameter in the additives and has CB of 45-100% where the CB is determined by the formula B.