Patents by Inventor Koshiro DATE

Koshiro DATE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor integrated circuit device
    Patent number: 12237266
    Abstract: An inverter cell having a logical function and a filler cell having no logical function are placed adjacent to each other. Nanowires of the filler cell are placed at the same positions as nanowires of the inverter cell in the Y direction. A p-type dummy transistor and n-type dummy transistor of the filler cell are respectively placed at the same levels as a p-type transistor and n-type transistor of the inverter cell in the Z direction.
    Type: Grant
    Filed: June 24, 2021
    Date of Patent: February 25, 2025
    Assignee: SOCIONEXT INC.
    Inventor: Koshiro Date
  • SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
    Publication number: 20220329235
    Abstract: A semiconductor integrated circuit device includes a flipflop circuit using vertical nanowire (VNW) FETs. A latch unit of the flipflop circuit includes: a feedback node; first p-type and n-type transistors each of which receives an input signal at one node and is connected to the feedback node at the other node; and second p-type and n-type transistors each connected to the feedback node at one node. In a standard cell, the tops of the first and second p-type and n-type transistors are connected to the feedback node.
    Type: Application
    Filed: June 27, 2022
    Publication date: October 13, 2022
    Inventor: Koshiro DATE
  • Semiconductor integrated circuit device
    Patent number: 11405023
    Abstract: A semiconductor integrated circuit device includes a flipflop circuit using vertical nanowire (VNW) FETs. A latch unit of the flipflop circuit includes: a feedback node; first p-type and n-type transistors each of which receives an input signal at one node and is connected to the feedback node at the other node; and second p-type and n-type transistors each connected to the feedback node at one node. In a standard cell, the tops of the first and second p-type and n-type transistors are connected to the feedback node.
    Type: Grant
    Filed: September 4, 2020
    Date of Patent: August 2, 2022
    Assignee: SOCIONEXT INC.
    Inventor: Koshiro Date
  • SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
    Publication number: 20210320065
    Abstract: An inverter cell having a logical function and a filler cell having no logical function are placed adjacent to each other. Nanowires of the filler cell are placed at the same positions as nanowires of the inverter cell in the Y direction. A p-type dummy transistor and n-type dummy transistor of the filler cell are respectively placed at the same levels as a p-type transistor and n-type transistor of the inverter cell in the Z direction.
    Type: Application
    Filed: June 24, 2021
    Publication date: October 14, 2021
    Inventor: Koshiro DATE
  • SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
    Publication number: 20200403605
    Abstract: A semiconductor integrated circuit device includes a flipflop circuit using vertical nanowire (VNW) FETs. A latch unit of the flipflop circuit includes: a feedback node; first p-type and n-type transistors each of which receives an input signal at one node and is connected to the feedback node at the other node; and second p-type and n-type transistors each connected to the feedback node at one node. In a standard cell, the tops of the first and second p-type and n-type transistors are connected to the feedback node.
    Type: Application
    Filed: September 4, 2020
    Publication date: December 24, 2020
    Inventor: Koshiro DATE