Abstract: A post-processing method and circuit (30) for correcting media noise errors and producing a corrected recovered data output signal (49) is disclosed for use in a sampled data read channel of a mass data storage device. The mass data storage device has a Viterbi detector (34) that receives actual sampled partial response target data (32) from a data medium of a mass data storage device. A recovered partial response target signal derived from the recovered data output signal and the sampled partial response target data is filtered to produce a filtered output signal (51). A threshold circuit (64) provides a threshold against which the filtered output signal is compared, and a predetermined value (60) is added to the filtered output signal when a predetermined error event pattern due to media noise or other transition jitter occurs in the recovered data output signal (35). The recovered data output signal is modified (70) when the filtered output signal exceeds the threshold of said threshold circuit (64).

Abstract: A post-processing method and circuit (30) for correcting media noise errors and producing a corrected recovered data output signal (49) is disclosed for use in a sampled data read channel of a mass data storage device. The mass data storage device has a Viterbi detector (34) that receives actual sampled partial response target data (32) from a data medium of a mass data storage device. A recovered partial response target signal derived from said recovered data output signal and said sampled partial response target data is filtered to produce a filtered output signal (51). A threshold circuit (64) provides a threshold against which said filtered output signal is compared, and a predetermined value (60) is added to the filtered output signal when a predetermined error event pattern due to media noise or other transition jitter occurs in said recovered data output signal (35). The recovered data output signal is modified (70) when said filtered output signal exceeds the threshold of said threshold circuit (64).

Abstract: A post-processor (10) is added to a PRML read channel in a mass data storage device for improving the error rate performance. The post-processor (10) includes dominant error pattern detection filters, which include a noise-whitening filter (32) and an error pattern matched filter (34). The post-processor improves performance by whitening the colored noise which bring the noise correlation loss, and by generating an error signal when one of the dominant error patterns is detected to enable the data output to be properly corrected.

Abstract: A method for writing data to a mass data storage device (10) includes applying a maximum transition run length code constraint to the data to be written, generating parity data based on the data, and inserting the parity data into the data to be written (5A-C). The parity data is used in conjunction with a post-processor (66) to detect and correct errors in the read back data.

Abstract: This invention relates to improvements in servo Gray code detection techniques in rotating data storage drives such as hard disk drives, or the like. The detection technique uses a rate ¼ Gray code servo signals equalized to a PR4 target, and a matched filter detector, and can realize a servo Gray code detector having high speed and performance. The Gray code detector (30) has an input (44) for receiving an input signal containing a Gray code that has been equalized to a PR4 target and a circuit (40-42, 46) for processing said input signal to determine a maximum Euclidean distance from zero to a value of the Gray code. The construction of the detector (30) depends upon the particular Gray code that is employed.

Abstract: A magnetic recording system with a rate 16/17(0,6/8) encoder/decoder modulation code. This modulation code has a low k constraint for synchronization of a road clock of the magnetic recording system. Furthermore, this magnetic recording system has a low hard error rate due to low 3- and 4-byte error propagation. The digital logic circuit for the encoder/decoder system is elegantly simple. Such simplicity reduces propagational delays and circuit size, as measured in number of logic gates. The modulation code is implemented with a decoder that includes a lower byte decoder and an upper byte decoder. An input of the upper byte decoder is in part coupled to and in part decoupled from the lower byte decoder. Similarly, an input of the lower byte decoder is in part coupled to and in part decoupled from the upper byte decoder.