Abstract: System and method for managing and specifying hardware implementation of a graphical program. A graphical program that implements an algorithm is stored in a memory of a computer system. The graphical program meets one or more first specified implementation requirements and is targeted for deployment to a programmable hardware element. A plurality of sets of descriptive directives are also stored in the memory, where the descriptive directives are associated with the graphical program and specify one or more additional specified implementation requirements, e.g., memory resource implementations, optimization directives, and so forth, where the additional directives result from programmatic and/or user-specification. Each set of descriptive directives is useable by a synthesis tool to generate a respective hardware configuration program for deployment to the graphical programmable hardware element.

Abstract: System and method for managing and specifying hardware implementation of a graphical program. A graphical program that implements an algorithm is stored in a memory of a computer system. The graphical program meets one or more first specified implementation requirements and is targeted for deployment to a programmable hardware element. A plurality of sets of descriptive directives are also stored in the memory, where the descriptive directives are associated with the graphical program and specify one or more additional specified implementation requirements, e.g., memory resource implementations, optimization directives, and so forth, where the additional directives result from programmatic and/or user-specification. Each set of descriptive directives is useable by a synthesis tool to generate a respective hardware configuration program for deployment to the graphical programmable hardware element.

Abstract: System and method for managing and specifying hardware implementation of a graphical program. A graphical program that implements an algorithm is stored in a memory of a computer system. The graphical program meets one or more first specified implementation requirements and is targeted for deployment to a programmable hardware element. A plurality of sets of descriptive directives are also stored in the memory, where the descriptive directives are associated with the graphical program and specify one or more additional specified implementation requirements, e.g., memory resource implementations, optimization directives, and so forth, where the additional directives result from programmatic and/or user-specification. Each set of descriptive directives is useable by a synthesis tool to generate a respective hardware configuration program for deployment to the graphical programmable hardware element.

Abstract: System and method for managing and specifying hardware implementation of a graphical program. A graphical program that implements an algorithm is stored in a memory of a computer system. The graphical program meets one or more first specified implementation requirements and is targeted for deployment to a programmable hardware element. A plurality of sets of descriptive directives are also stored in the memory, where the descriptive directives are associated with the graphical program and specify one or more additional specified implementation requirements, e.g., memory resource implementations, optimization directives, and so forth, where the additional directives result from programmatic and/or user-specification. Each set of descriptive directives is useable by a synthesis tool to generate a respective hardware configuration program for deployment to the graphical programmable hardware element.

Abstract: Testing a first graphical program intended for implementation on a programmable hardware element. The first graphical program may be stored. The first graphical program may include a first plurality of nodes connected by lines which visually specify first functionality. The first graphical program may be intended for implementation by the programmable hardware element. A second graphical program may be stored which visually specifies testing functionality for the first graphical program. The second graphical program may be executable by a host computer to simulate input to the programmable hardware element when configured by the first graphical program. The first graphical program and the second graphical program may be executed (e.g., by a host computer) to test the first functionality when implemented by the programmable hardware element. During execution, simulated outputs may be monitored.

Abstract: Testing a first graphical program intended for implementation on a programmable hardware element. The first graphical program may be stored. The first graphical program may include a first plurality of nodes connected by lines which visually specify first functionality. The first graphical program may be intended for implementation by the programmable hardware element. A second graphical program may be stored which visually specifies testing functionality for the first graphical program. The second graphical program may be executable by a host computer to simulate input to the programmable hardware element when configured by the first graphical program. The first graphical program and the second graphical program may be executed (e.g., by a host computer) to test the first functionality when implemented by the programmable hardware element. During execution, simulated outputs may be monitored.

Abstract: System and method for designing a circuit. At least one graphical program comprising a plurality of interconnected nodes that visually indicate functionality of the graphical program is selected in response to user input. At least one pre-defined hardware configuration program (HCP) is selected from a plurality of pre-defined HCPs in response to user input, where the selected at least one pre-defined HCP specifies a fixed functionality, including interface functionality for communicating with the at least one graphical program when implemented on the circuit. At least a portion of a netlist is generated based on the at least one graphical program and the at least one selected pre-defined HCP, where the netlist is usable to configure a circuit, wherein a first portion of the circuit implements the functionality of the graphical program and a second portion of the circuit implements the fixed functionality.

Abstract: System and method for designing a circuit. At least one graphical program comprising a plurality of interconnected nodes that visually indicate functionality of the graphical program is selected in response to user input. At least one pre-defined hardware configuration program (HCP) is selected from a plurality of pre-defined HCPs in response to user input, where the selected at least one pre-defined HCP specifies a fixed functionality, including interface functionality for communicating with the at least one graphical program when implemented on the circuit. At least a portion of a netlist is generated based on the at least one graphical program and the at least one selected pre-defined HCP, where the netlist is usable to configure a circuit, wherein a first portion of the circuit implements the functionality of the graphical program and a second portion of the circuit implements the fixed functionality.

Abstract: An electronic instrument which has a virtual magnifying symbol capable of magnifying a portion of the instrument's signal waveform in a single window of the instrument display. The user is able to position the virtual magnifying symbol with knobs, buttons, or, more preferably, with a pointer, such as a mouse, digital pen, or touch screen. The virtual magnifying symbol can be employed at all times during display of the signal waveform. In the preferred embodiment, the virtual magnifying symbol is a magnifying glass. The user centers the desired portion of the signal waveform within the virtual lens of the magnifying glass, then magnifies the desired portion. Thus the instrument with the virtual magnifying glass of the present invention provides an innovative solution for simultaneously magnifying a portion of the instrument's signal waveform within the context of the entire signal waveform.

Abstract: An application programming interface (API) for synchronizing multiple devices in a system. The API includes a plurality of functions invocable in a program to synchronize multiple devices, where each function is executable to perform a respective functionality related to synchronizing the devices, and at least one of the functions is executable to access a plurality of instrument drivers corresponding respectively to the plurality of devices to synchronize the plurality of devices. In synchronizing the plurality of devices, the functions determine a trigger clock signal for each of the plurality of devices, and synchronize the plurality of devices based on the determined trigger clock signals. The API also includes a plurality of attributes corresponding to respective properties of the system related to synchronization of the devices, including one or more trigger attributes and/or one or more trigger clock attributes for each of the devices. The API representations may be text-based and/or graphical.

Abstract: System and method for reporting invalid parameter values for a system. An invalid value of a parameter is detected, and information related to the detection determined, including one or more valid values for the parameter, and optionally, an identifier (ID) of the parameter, the invalid value of the parameter, and/or contextual information related to the detection, e.g., a function ID and/or device ID indicating where the detection occurred, an error ID corresponding to the detection, a time value indicating when the detection occurred, and/or a text description of the error and/or parameter. The detection of the invalid value of the parameter is reported, optionally including some or all of the determined information, and the valid values for the parameter displayed. Input, e.g., user input, may optionally be received specifying a new valid value for the parameter, and the parameter set to the specified value.

Abstract: An application programming interface (API) for synchronizing multiple devices in a system. The API includes a plurality of functions invocable in a program to synchronize multiple devices, where each function is executable to perform a respective functionality related to synchronizing the devices, and at least one of the functions is executable to access a plurality of instrument drivers corresponding respectively to the plurality of devices to synchronize the plurality of devices. In synchronizing the plurality of devices, the functions determine a trigger clock signal for each of the plurality of devices, and synchronize the plurality of devices based on the determined trigger clock signals. The API also includes a plurality of attributes corresponding to respective properties of the system related to synchronization of the devices, including one or more trigger attributes and/or one or more trigger clock attributes for each of the devices. The API representations may be text-based and/or graphical.

Abstract: System and method for reporting invalid parameter values for a system. An invalid value of a parameter is detected, and information related to the detection determined, including one or more valid values for the parameter, and optionally, an identifier (ID) of the parameter, the invalid value of the parameter, and/or contextual information related to the detection, e.g., a function ID and/or device ID indicating where the detection occurred, an error ID corresponding to the detection, a time value indicating when the detection occurred, and/or a text description of the error and/or parameter. The detection of the invalid value of the parameter is reported, optionally including some or all of the determined information, and the valid values for the parameter displayed. Input, e.g., user input, may optionally be received specifying a new valid value for the parameter, and the parameter set to the specified value.

Abstract: An electronic instrument which has a virtual magnifying symbol capable of magnifying a portion of the instrument's signal waveform in a single window of the instrument display. The user is able to position the virtual magnifying symbol with knobs, buttons, or, more preferably, with a pointer, such as a mouse, digital pen, or touch screen. The virtual magnifying symbol can be employed at all times during display of the signal waveform. In the preferred embodiment, the virtual magnifying symbol is a magnifying glass. The user centers the desired portion of the signal waveform within the virtual lens of the magnifying glass, then magnifies the desired portion. Thus the instrument with the virtual magnifying glass of the present invention provides an innovative solution for simultaneously magnifying a portion of the instrument's signal waveform within the context of the entire signal waveform.

Abstract: A counter circuit with multiple registers for eliminating reprogramming delays and for providing seamless switching between timing signals. In a first embodiment, two registers are preloaded with values and control logic chooses between the registers for loading a counter. The counter asserts a terminal count signal to output logic, which correspondingly asserts a convert pulse to an analog measuring circuit. The control logic receives start and stop signals and the terminal count signal, where the control logic controls operation accordingly. In this manner, a delay value is initially loaded into the counter to provide an initial delay period upon receiving the start signal, and then a scan rate value is continually loaded into the counter from another register thereafter for defining the scan rate until the start signal is received.

Abstract: A method and apparatus for programming hardware registers using a database defining each hardware register and associated bit fields of the registers, input code including bit field write (BFW) commands identifying bit fields corresponding values to program into the bit fields and defining an array of software copies of the hardware registers, and a preprocessor for writing the appropriate code to program the hardware registers. The database provides the name, size and address of each register and the names and sizes of associated bit fields within each register. The preprocessor generates output source code by replacing the BFW commands with code to manipulate software copies of the hardware registers and to write the software copies to the hardware registers. The output source code identifies each of the affected registers and writing appropriate code to access the register only once per BFW command.

Abstract: A latency error detection circuit including two cascaded latches receiving a clock signal from a measuring system upon the occurrence of an event and correspondingly asserting a bit to a processing system, and a circuit for clearing the first latch after the processing system acknowledges detecting the bit being asserted. If the second latch is clocked before the first latch is cleared, the second latch sets an error bit indicating a latency error condition. The processor system monitors the error bit to determine whether a latency error has occurred.