Patents by Inventor Kostantin Godin
Kostantin Godin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20150149446Abstract: Circuitry for a computing system includes a memory arrangement having at least one memory management unit and at least one processor. The at least one processor is arranged to issue a memory query to the memory management unit. The memory management unit is arranged to provide a query result in response to the memory query directly to the processor via a data connection.Type: ApplicationFiled: July 27, 2012Publication date: May 28, 2015Applicant: Freescale Semiconductor, Inc.Inventors: Ziv Zamsky, Dmitry Flat, Kostantin Godin, Itay Peled
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Patent number: 8281080Abstract: A system and method for modifying an information unit, the method includes the following stages: (i) receiving, over a first bus, a request to initiate a snooping type atomic operation associated with at least one information unit located at a first address of a memory module; (ii) providing the information unit over the first bus; (iii) attempting to complete the snooping type atomic operation of an updated information unit; and (iv) defining the atomic operation as a failed atomic operation if during at least one stage of receiving, providing and attempting, the first address was locked as a result of a locking type atomic operation.Type: GrantFiled: September 2, 2004Date of Patent: October 2, 2012Assignee: Freescale Semiconductor, Inc.Inventors: Kostantin Godin, Moshe Anschel, Uri Dayan, Dvir Rune R Peleg
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Patent number: 8117400Abstract: A device and a method for fetching an information unit, the method includes: receiving a request to execute a write through cacheable operation of the information unit; emptying a fetch unit from data, wherein the fetch unit is connected to a cache module and to a high level memory unit; determining, when the fetch unit is empty, whether the cache module stores an older version of the information unit; and selectively writing the information unit to the cache module in response to the cache module in response to the determination.Type: GrantFiled: October 20, 2006Date of Patent: February 14, 2012Assignee: Freescale Semiconductor, Inc.Inventors: Ziv Zamsky, Moshe Anschel, Alon Eldar, Dmitry Flat, Kostantin Godin, Itay Peled, Dvir Peleg
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Patent number: 8041899Abstract: A write back allocate system that includes: (i) a store request circuit; (ii) a processor, adapted to generate a store request that comprises an information unit and an information unit address; and (iii) a cache module, connected to the store request circuit and to a high level memory unit. A single cache module line includes multiple segments, each segment is adapted to store a single information unit. A content of a cache module line is retrieved from the high level memory unit by generating a fetch burst that includes multiple segment fetch operations. The store request circuit includes a snooper and a controller. The snooper detects a portion of an address of a cache segment of a cache line that is being fetched during a fetch burst. The controller is adapted to request from the cache module to receive the information unit before a completion of the fetch burst if the portion of the address of the cache segment matches a corresponding portion of the information unit address.Type: GrantFiled: July 29, 2008Date of Patent: October 18, 2011Assignee: Freescale Semiconductor, Inc.Inventors: Kostantin Godin, Roman Landa, Itay Peled, Yakov Tokar, Ziv Zamsky
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Patent number: 8006015Abstract: A device and a method for managing access requests, the method includes: (i) receiving, from a master component coupled to a master bus, multiple access requests to access a slave component over a pipelined slave bus; acknowledging a received access request if: (a) at least an inter-access request delay period lapsed from a last acknowledgement of an access request; (b) an amount of pending acknowledged access requests is below a threshold; wherein the threshold is determined in response to a pipeline depth of the pipelined slave bus; (c) the received access request is valid; wherein a validity of an access request is responsive to a reception of an access request cancellation request; and (ii) providing information from the slave component, in response to at least one acknowledged access request.Type: GrantFiled: November 8, 2006Date of Patent: August 23, 2011Assignee: Freescale Semiconductor, Inc.Inventors: Yaki Devilla, Moshe Anschel, Kostantin Godin, Amit Gur, Itay Peled
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Publication number: 20110040912Abstract: Apparatus and method for bus matching. The method includes: receiving data transfer characteristics at a first endian mode and at a second endian mode; determining a connectivity of multiple devices to an interfacing bus in response to the data transfer characteristics and in response to a relationship between a width of the interfacing bus and a width of each device interface; wherein at least one device interface is connected in parallel to multiple interfacing bus portions; and configuring a control logic such as to provide control signals representative of a transfer of data over the interfacing bus; whereas the control logic is configured in response to the connectivity.Type: ApplicationFiled: September 10, 2004Publication date: February 17, 2011Applicant: Freescale SemiconductorInventors: Kostantin Godin, Moshe Anschel, Jacob Efrat, Itay Peled, Reuven Badash, Asher Bastaker, Dvir Rune Peleg, Ziv Zamsky
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Publication number: 20100325366Abstract: A device and a method for fetching an information unit, the method includes: receiving a request to execute a write through cacheable operation of the information unit; emptying a fetch unit from data, wherein the fetch unit is connected to a cache module and to a high level memory unit; determining, when the fetch unit is empty, whether the cache module stores an older version of the information unit; and selectively writing the information unit to the cache module in response to the cache module in response to the determination.Type: ApplicationFiled: October 20, 2006Publication date: December 23, 2010Inventors: Ziv Zamsky, Moshe Anschel, Alon Eldar, Dmitry Flat, Kostantin Godin, Itay Peled, Dvir Peleg
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Publication number: 20100250806Abstract: A device and a method for managing access requests, the method includes: (i) receiving, from a master component coupled to a master bus, multiple access requests to access a slave component over a pipelined slave bus; acknowledging a received access request if: (a) at least an inter-access request delay period lapsed from a last acknowledgement of an access request; (b) an amount of pending acknowledged access requests is below a threshold; wherein the threshold is determined in response to a pipeline depth of the pipelined slave bus; (c) the received access request is valid; wherein a validity of an access request is responsive to a reception of an access request cancellation request; and (ii) providing information from the slave component, in response to at least one acknowledged access request.Type: ApplicationFiled: November 8, 2006Publication date: September 30, 2010Applicant: Freescale Semiconductor, Inc.Inventors: Yaki Devilla, Moshe Anschel, Kostantin Godin, Amit Gur, Italy Peled
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Publication number: 20100030974Abstract: A write back allocate system that includes: (i) a store request circuit; (ii) a processor, adapted to generate a store request that comprises an information unit and an information unit address; and (iii) a cache module, connected to the store request circuit and to a high level memory unit. A single cache module line includes multiple segments, each segment is adapted to store a single information unit. A content of a cache module line is retrieved from the high level memory unit by generating a fetch burst that includes multiple segment fetch operations. The store request circuit includes a snooper and a controller. The snooper detects a portion of an address of a cache segment of a cache line that is being fetched during a fetch burst. The controller is adapted to request from the cache module to receive the information unit before a completion of the fetch burst if the portion of the address of the cache segment matches a corresponding portion of the information unit address.Type: ApplicationFiled: July 29, 2008Publication date: February 4, 2010Inventors: Kostantin Godin, Roman Landa, Itay Peled, Yakov Tokar, Ziv Zamsky
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Patent number: 7620760Abstract: A device that includes: a first bus, connected between a first logic and a first circuit; a group of second buses connected between the first logic and between multiple non-high impedance circuit access logics associated with multiple circuits; wherein each circuit access logic is adapted to: (i) provide to the first logic, a circuit write value during a circuit writing period and during an idle period that follows the circuit writing period and ends when another circuit is allowed to write; and (ii) provide a default value when another circuit is allowed to write; and wherein the first logic is adapted to alter a state of the first bus in response to a change between two consecutive circuit write values.Type: GrantFiled: February 7, 2005Date of Patent: November 17, 2009Assignee: Freescale Semiconductor, Inc.Inventors: Kostantin Godin, Moshe Anschel, Yacov Efrat, Leonid Rabinovich, Noam Sivan, Eitan Zmora, Ziv Zamsky
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Patent number: 7434009Abstract: Apparatus and method for providing information to a cache module, the apparatus includes: (i) at least one processor, connected to the cache module, for initiating a first and second requests to retrieve, from the cache module, a first and a second data unit; (ii) logic, adapted to receive the requests and determine if the first and second data units are mandatory data units; and (iii) a controller, connected to the cache module, adapted to initiate a single fetch burst if a memory space retrievable during the single fetch burst comprises the first and second mandatory data units, and adapted to initiate multiple fetch bursts if a memory space retrievable during a single fetch burst does not comprise the first and the second mandatory data units.Type: GrantFiled: September 30, 2004Date of Patent: October 7, 2008Assignee: Freescale Semiconductor, Inc.Inventors: Kostantin Godin, Moshe Anschel, Yacov Efrat, Zvika Rozenshein, Ziv Zamsky
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Publication number: 20080140894Abstract: A device that includes: a first bus, connected between a first logic and a first circuit; a group of second buses connected between the first logic and between multiple non-high impedance circuit access logics associated with multiple circuits; wherein each circuit access logic is adapted to: (i) provide to the first logic, a circuit write value during a circuit writing period and during an idle period that follows the circuit writing period and ends when another circuit is allowed to write; and (ii) provide a default value when another circuit is allowed to write; and wherein the first logic is adapted to alter a state of the first bus in response to a change between two consecutive circuit write values.Type: ApplicationFiled: February 7, 2005Publication date: June 12, 2008Applicant: Freescale Semiconductor, IncInventors: Kostantin Godin, Mosche Anschel, Yacov Efrat, Leonid Rabinovich, Noam Sivan, Eitan Zmora, Ziv Zamsky
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Publication number: 20060069877Abstract: Apparatus and method for providing information to a cache module, the apparatus includes: (i) at least one processor, connected to the cache module, for initiating a first and second requests to retrieve, from the cache module, a first and a second data unit; (ii) logic, adapted to receive the requests and determine if the first and second data units are mandatory data units; and (iii) a controller, connected to the cache module, adapted to initiate a single fetch burst if a memory space retrievable during the single fetch burst comprises the first and second mandatory data units, and adapted to initiate multiple fetch bursts if a memory space retrievable during a single fetch burst does not comprise the first and the second mandatory data units.Type: ApplicationFiled: September 30, 2004Publication date: March 30, 2006Inventors: Kostantin Godin, Moshe Anschel, Yacov Efrat, Zvika Rozenshein, Ziv Zamsky
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Publication number: 20060047917Abstract: A system and method for modifying an information unit, the method includes the following stages: (i) receiving, over a first bus, a request to initiate a snooping type atomic operation associated with at least one information unit located at a first address of a memory module; (ii) providing the information unit over the first bus; (iii) attempting to complete the snooping type atomic operation of an updated information unit; and (iv) defining the atomic operation as a failed atomic operation if during at least one stage of receiving, providing and attempting, the first address was locked as a result of a locking type atomic operation.Type: ApplicationFiled: September 2, 2004Publication date: March 2, 2006Inventors: Kostantin Godin, Moshe Anschel, Uri Dayan, Dvir Peleg