Patents by Inventor Kostantinos D. Christidis

Kostantinos D. Christidis has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Aware Cache Replacement Policy
    Publication number: 20170168957
    Abstract: An aware cache replacement policy increases the length of in-page bursts of cache eviction memory requests and promotes bank-rotation to reduce the likelihood of memory bank-conflicts as compared to other cache replacement policies. The aware cache replacement policy increases the amount of valid data on the memory bus and reduces the impact of main memory precharge and activate times by evicting cache blocks in bursts based on temporal and spatial locality according to requesting thread and/or memory structure.
    Type: Application
    Filed: December 10, 2015
    Publication date: June 15, 2017
    Inventor: Kostantinos D. Christidis
  • Translation layer for controlling bus access
    Patent number: 9588734
    Abstract: A translation layer includes a plurality of first buffers and a controller to assert one or more ready signals corresponding to one or more of the plurality of first buffers in response to the one or more of the plurality of first buffers being less than full. The one or more of the plurality of first buffers receives data or control information from one or more corresponding components in response to the ready signal being asserted concurrently with one or more valid signals asserted by the one or more corresponding components.
    Type: Grant
    Filed: June 13, 2014
    Date of Patent: March 7, 2017
    Assignee: ATI Technologies ULC
    Inventor: Kostantinos D. Christidis
  • TRANSLATION LAYER FOR CONTROLLING BUS ACCESS
    Publication number: 20150363166
    Abstract: A translation layer includes a plurality of first buffers and a controller to assert one or more ready signals corresponding to one or more of the plurality of first buffers in response to the one or more of the plurality of first buffers being less than full. The one or more of the plurality of first buffers receives data or control information from one or more corresponding components in response to the ready signal being asserted concurrently with one or more valid signals asserted by the one or more corresponding components.
    Type: Application
    Filed: June 13, 2014
    Publication date: December 17, 2015
    Inventor: Kostantinos D. Christidis