Patents by Inventor Kostantinos Danny Christidis
Kostantinos Danny Christidis has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11947473Abstract: Systems, apparatuses, and methods for implementing duplicated registers for access by initiators across multiple semiconductor dies are disclosed. A system includes multiple initiators on multiple semiconductor dies of a chiplet processor. One of the semiconductor dies is the master die, and this master die has copies of registers which can be accessed by the multiple initiators on the multiple semiconductor dies. When a given initiator on a given secondary die generates a register access, the register access is routed to the master die and a particular duplicate copy of the register maintained for the given secondary die. From the point of view of software, the multiple semiconductor dies appear as a single die, and the multiple initiators appear as a single initiator. Multiple types of registers can be maintained by the master die, with a flush register being one of the register types.Type: GrantFiled: October 12, 2021Date of Patent: April 2, 2024Assignees: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Haikun Dong, Kostantinos Danny Christidis, Ling-Ling Wang, MinHua Wu, Gaojian Cong, Rui Wang
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Patent number: 11853231Abstract: Apparatuses, systems and methods for routing requests and responses targeting a shared resource. A queue in a communication fabric is located in a path between the requesters and a shared resource. In some embodiments, the shared resource is a shared address translation cache stored in an endpoint. The physical channel between the queue and the shared resource supports multiple virtual channels. The queue assigns at least one entry to each virtual channel of a group of virtual channels where the group includes a virtual channel for each address translation request type from a single requester of the multiple requesters. When the at least one entry for a given requester is de-allocated, the queue allocates this entry only with requests from the assigned virtual channel even if the empty entry is the only available entry of the queue.Type: GrantFiled: June 24, 2021Date of Patent: December 26, 2023Assignee: ATI Technologies ULCInventor: Kostantinos Danny Christidis
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Publication number: 20230342307Abstract: Apparatuses, systems and methods for routing requests and responses targeting a shared resource. A queue in a communication fabric is located in a path between the requesters and a shared resource. In some embodiments, the shared resource is a shared address translation cache stored in an endpoint. The physical channel between the queue and the shared resource supports multiple virtual channels. The queue assigns at least one entry to each virtual channel of a group of virtual channels where the group includes a virtual channel for each address translation request type from a single requester of the multiple requesters. When the at least one entry for a given requester is de-allocated, the queue allocates this entry only with requests from the assigned virtual channel even if the empty entry is the only available entry of the queue.Type: ApplicationFiled: June 13, 2023Publication date: October 26, 2023Inventor: Kostantinos Danny Christidis
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Publication number: 20230115819Abstract: Systems, apparatuses, and methods for implementing duplicated registers for access by initiators across multiple semiconductor dies are disclosed. A system includes multiple initiators on multiple semiconductor dies of a chiplet processor. One of the semiconductor dies is the master die, and this master die has copies of registers which can be accessed by the multiple initiators on the multiple semiconductor dies. When a given initiator on a given secondary die generates a register access, the register access is routed to the master die and a particular duplicate copy of the register maintained for the given secondary die. From the point of view of software, the multiple semiconductor dies appear as a single die, and the multiple initiators appear as a single initiator. Multiple types of registers can be maintained by the master die, with a flush register being one of the register types.Type: ApplicationFiled: October 12, 2021Publication date: April 13, 2023Inventors: HaiKun Dong, Kostantinos Danny Christidis, Ling-Ling Wang, MinHua Wu, Gaojian Cong, Rui Wang
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Publication number: 20230034633Abstract: A data processor includes a plurality of requestors, a plurality of responders, and a data fabric. The data fabric is for routing requests between the plurality of requestors and the plurality of responders and has a plurality of non-operational power states including a normal C-state and a light-weight C-state. The light-weight C-state has lower entry and exit latencies than the normal C-state. The data fabric monitors traffic through the data fabric and places the data fabric in the light-weight C-state in response to detecting an idle traffic state.Type: ApplicationFiled: July 30, 2021Publication date: February 2, 2023Applicants: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Benjamin Tsien, Alexander J. Branover, Dilip Jha, James R. Magro, MingLiang Lin, Kostantinos Danny Christidis, Hui Zhou
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Publication number: 20230009970Abstract: An apparatus and method for providing efficient power management for data transfer protocols between components. A source generates requests and a destination services the requests. The source and destination support a communication protocol that includes both a transfer channel and one or more transaction channels for each type of request. The source and destination rely on a valid signal and a ready signal of the transfer channels to autonomously manage power consumption. The source and destination remove any dependencies on an external power manager and make it unnecessary to add signal extensions to the communication protocol to support power management.Type: ApplicationFiled: July 9, 2021Publication date: January 12, 2023Inventors: Chi Yan Herburt Shek, Kostantinos Danny Christidis
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Publication number: 20220417206Abstract: Apparatuses, systems and methods for routing requests and responses targeting a shared resource. A queue in a communication fabric is located in a path between the requesters and a shared resource. In some embodiments, the shared resource is a shared address translation cache stored in an endpoint. The physical channel between the queue and the shared resource supports multiple virtual channels. The queue assigns at least one entry to each virtual channel of a group of virtual channels where the group includes a virtual channel for each address translation request type from a single requester of the multiple requesters. When the at least one entry for a given requester is de-allocated, the queue allocates this entry only with requests from the assigned virtual channel even if the empty entry is the only available entry of the queue.Type: ApplicationFiled: June 24, 2021Publication date: December 29, 2022Inventor: Kostantinos Danny Christidis
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Patent number: 11275632Abstract: Systems, apparatuses, and methods for implementing a broadcast read response protocol are disclosed. A computing system includes a plurality of processing engines coupled to a memory subsystem. A first processing engine executes a read and broadcast response command, wherein the read and broadcast response command targets first data at a first address in the memory subsystem. One or more other processing engines execute a wait command to wait to receive the first data requested by the first processing engine. After receiving the first data from the memory subsystem, the plurality of processing engines process the first data as part of completing a first operation. In one implementation, the first operation is implementing a given layer of a machine learning model. In one implementation, the given layer is a convolutional layer of a neural network.Type: GrantFiled: October 26, 2018Date of Patent: March 15, 2022Assignees: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Kostantinos Danny Christidis, Lei Zhang, Sateesh Lagudu, Purushotham Niranjan Dasiga
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Publication number: 20200089550Abstract: Systems, apparatuses, and methods for implementing a broadcast read response protocol are disclosed. A computing system includes a plurality of processing engines coupled to a memory subsystem. A first processing engine executes a read and broadcast response command, wherein the read and broadcast response command targets first data at a first address in the memory subsystem. One or more other processing engines execute a wait command to wait to receive the first data requested by the first processing engine. After receiving the first data from the memory subsystem, the plurality of processing engines process the first data as part of completing a first operation. In one implementation, the first operation is implementing a given layer of a machine learning model. In one implementation, the given layer is a convolutional layer of a neural network.Type: ApplicationFiled: October 26, 2018Publication date: March 19, 2020Inventors: Kostantinos Danny Christidis, Lei Zhang, Sateesh Lagudu, Purushotham Niranjan Dasiga
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Patent number: 10417140Abstract: Techniques are provided for using a translation lookaside buffer to provide low latency memory address translations for data streams. Clients of a memory system first prepare the address translation cache hierarchy by requesting that a translation pre-fetch stream is initialized. After the translation pre-fetch stream is initialized, the cache hierarchy returns an acknowledgment of completion to the client, which then begins to access memory. Pre-fetch streams are specified in terms of address ranges and are performed for large contiguous portions of the virtual memory address space.Type: GrantFiled: February 24, 2017Date of Patent: September 17, 2019Assignees: ADVANCED MICRO DEVICES, INC., ATI TECHNOLOGIES ULCInventors: Wade K. Smith, Kostantinos Danny Christidis
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Patent number: 10198358Abstract: Apparatuses, computer readable mediums, and methods of processor unit testing using cache resident testing are disclosed. The method may include loading a test program in a cache on a chip comprising one or more processor units. The method may include the one or more processor units executing the test program to generate one or more results. The method may include redirecting a first memory reference to the cache, wherein the first memory reference is generated during the execution of the test program. The method may include determining whether the one or more generated results match one or more test results. The method may include redirecting a memory request to a memory location resident in the cache if the memory request includes a memory location not resident in the cache. The method may include redirecting a memory request to the cache if the memory request is not directed to the cache.Type: GrantFiled: April 2, 2014Date of Patent: February 5, 2019Assignees: ADVANCED MICRO DEVICES, INC., ATI TECHNOLOGIES ULCInventors: Angel E. Socarras, Kostantinos Danny Christidis, Curtis Alan Gilgan, Alexander Fuad Ashkar
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Patent number: 10152434Abstract: A system and method for efficient arbitration of memory access requests are described. One or more functional units generate memory access requests for a partitioned memory. An arbitration unit stores the generated requests and selects a given one of the stored requests. The arbitration unit identifies a given partition of the memory which stores a memory location targeted by the selected request. The arbitration unit determines whether one or more other stored requests access memory locations in the given partition. The arbitration unit sends each of the selected memory access request and the identified one or more other memory access requests to the memory to be serviced out of order.Type: GrantFiled: December 20, 2016Date of Patent: December 11, 2018Assignees: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Rostyslav Kyrychynskyi, Anthony Asaro, Kostantinos Danny Christidis, Mark Fowler, Michael J. Mantor, Robert Scott Hartog
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Patent number: 10114761Abstract: Techniques are provided for managing address translation request traffic where memory access requests can be made with differing quality-of-service levels, which specify latency and/or bandwidth requirements. The techniques involve translation lookaside buffers. Within the translation lookaside buffers, certain resources are reserved for specific quality-of-service levels. More specifically, translation lookaside buffer slots, which store the actual translations, as well as finite state machines in a work queue, are reserved for specific quality-of-service levels. The translation lookaside buffer receives multiple requests for address translation. The translation lookaside buffer selects requests having the highest quality-of-service level for which an available finite state machine is available.Type: GrantFiled: February 24, 2017Date of Patent: October 30, 2018Assignees: ATI TECHNOLOGIES ULC., ADVANCED MICRO DEVICES, INC.Inventors: Wade K. Smith, Kostantinos Danny Christidis
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Publication number: 20180246815Abstract: Techniques are provided for managing address translation request traffic where memory access requests can be made with differing quality-of-service levels, which specify latency and/or bandwidth requirements. The techniques involve translation lookaside buffers. Within the translation lookaside buffers, certain resources are reserved for specific quality-of-service levels. More specifically, translation lookaside buffer slots, which store the actual translations, as well as finite state machines in a work queue, are reserved for specific quality-of-service levels. The translation lookaside buffer receives multiple requests for address translation. The translation lookaside buffer selects requests having the highest quality-of-service level for which an available finite state machine is available.Type: ApplicationFiled: February 24, 2017Publication date: August 30, 2018Applicants: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Wade K. Smith, Kostantinos Danny Christidis
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Publication number: 20180246816Abstract: Techniques are provided for using a translation lookaside buffer to provide low latency memory address translations for data streams. Clients of a memory system first prepare the address translation cache hierarchy by requesting that a translation pre-fetch stream is initialized. After the translation pre-fetch stream is initialized, the cache hierarchy returns an acknowledgment of completion to the client, which then begins to access memory. Pre-fetch streams are specified in terms of address ranges and are performed for large contiguous portions of the virtual memory address space.Type: ApplicationFiled: February 24, 2017Publication date: August 30, 2018Applicants: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Wade K. Smith, Kostantinos Danny Christidis
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Publication number: 20180173649Abstract: A system and method for efficient arbitration of memory access requests are described. One or more functional units generate memory access requests for a partitioned memory. An arbitration unit stores the generated requests and selects a given one of the stored requests. The arbitration unit identifies a given partition of the memory which stores a memory location targeted by the selected request. The arbitration unit determines whether one or more other stored requests access memory locations in the given partition. The arbitration unit sends each of the selected memory access request and the identified one or more other memory access requests to the memory to be serviced out of order.Type: ApplicationFiled: December 20, 2016Publication date: June 21, 2018Inventors: Rostyslav Kyrychynskyi, Anthony Asaro, Kostantinos Danny Christidis, Mark Fowler, Michael J. Mantor, Robert Scott Hartog
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Publication number: 20150286573Abstract: Apparatuses, computer readable mediums, and methods of processor unit testing using cache resident testing are disclosed. The method may include loading a test program in a cache on a chip comprising one or more processor units. The method may include the one or more processor units executing the test program to generate one or more results. The method may include redirecting a first memory reference to the cache, wherein the first memory reference is generated during the execution of the test program. The method may include determining whether the one or more generated results match one or more test results. The method may include redirecting a memory request to a memory location resident in the cache if the memory request includes a memory location not resident in the cache. The method may include redirecting a memory request to the cache if the memory request is not directed to the cache.Type: ApplicationFiled: April 2, 2014Publication date: October 8, 2015Applicants: ATI TECHNOLOGIES ULC, ADVANCED MICRO DEVICES, INC.Inventors: Angel E. Socarras, Kostantinos Danny Christidis, Curtis Alan Gilgan, Alexander Fuad Ashkar