Patents by Inventor Kosuke Asano

Kosuke Asano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12673620
    Abstract: An in-vehicle system includes: an in-vehicle device that includes a device main unit with a panel provided on a front surface thereof; a cluster panel that is arranged on the panel; a positioning mechanism which mutually positions the panel and the cluster panel; a vehicle mounting bracket that is fixed to the cluster panel and the device main unit, and that is mounted on a vehicle; and multiple mounting holes that are aligned in a vehicle longitudinal direction in the vehicle mounting bracket and which correspond to screw holes which are provided on a side surface of the device main unit, each of which has a larger diameter than each of screw holes, and a vertical diameter of the mounting hole is formed to be larger as the mounting hole is positioned towards a vehicle front side.
    Type: Grant
    Filed: December 9, 2024
    Date of Patent: July 7, 2026
    Assignee: JVCKENWOOD Corporation
    Inventors: Kosuke Asano, Yuki Takahashi
  • Publication number: 20260173787
    Abstract: A manufacturing method for a semiconductor device includes forming a depression in an interlayer dielectric film placed on a semiconductor substrate, forming a planarized film made of a first cured product of a first curable composition on the interlayer dielectric film so as to cover the depression, forming, on the planarized film, a pattern made of a second cured product of a second curable composition and having an opening on the depression, etching the planarized film by using the pattern so as to form a trench in the first cured product in the depression, forming a metal film on the interlayer dielectric film so as to fill the trench with a metal, and polishing the metal film by a CMP method so as to leave a metal pattern in the trench.
    Type: Application
    Filed: December 8, 2025
    Publication date: June 18, 2026
    Inventors: TETSUYA KIMURA, KOSUKE ASANO
  • Publication number: 20260173838
    Abstract: A semiconductor device includes a first substrate and a second substrate. The first substrate includes a first semiconductor substrate, and a first wiring structure having an interlayer dielectric film containing a cured product of a curable composition, a trench provided in the cured product, and a first metal pattern filled in the trench. The second substrate includes a second semiconductor substrate, and a second wiring structure having a second metal pattern. The first metal pattern is joined to the second metal pattern.
    Type: Application
    Filed: December 8, 2025
    Publication date: June 18, 2026
    Inventors: TETSUYA KIMURA, KOSUKE ASANO
  • Publication number: 20260150420
    Abstract: A device in which a plurality of pixels are arranged in a substrate is provided. Each of the plurality of pixels includes a portion, and an element configured to function as a light converging element and a color filter, the plurality of pixels include a first pixel and a second pixel arranged adjacent to each other, the element of the first pixel and the element of the second pixel transmit light components of different colors, respectively, and are in contact with each other, and a contact surface where the element of the first pixel and the element of the second pixel contact is tilted with respect to a normal direction of a surface of the substrate.
    Type: Application
    Filed: November 24, 2025
    Publication date: May 28, 2026
    Inventors: KOSUKE ASANO, TETSUYA KIMURA
  • Publication number: 20260150423
    Abstract: A photoelectric conversion device including: a semiconductor layer having a first main surface and a second main surface and including a first photoelectric conversion element and a second photoelectric conversion element adjacent to each other; and an element isolation portion arranged to electrically isolate the first photoelectric conversion element and the second photoelectric conversion element, is provided. A cured product of a curable composition is arranged on the first main surface, a plurality of trenches extending from a surface of the cured product toward the first main surface are provided in the cured product, and the plurality of trenches include a first trench constituting a scattering diffraction structure arranged to overlap the first photoelectric conversion element, and a second trench constituting an isolation structure arranged to overlap the element isolation portion.
    Type: Application
    Filed: November 14, 2025
    Publication date: May 28, 2026
    Inventors: KOSUKE ASANO, TETSUYA KIMURA
  • Publication number: 20260136813
    Abstract: A light emitting device includes a plurality of sub-pixels including first and second sub-pixels. The first sub-pixel includes a first reflecting member below a first lower electrode, and the second sub-pixel includes a second reflecting member below a second lower electrode. The device includes an insulating film arranged below the lower electrodes of the plurality of sub-pixels so as to cover the first reflecting member and the second reflecting member. The insulating film includes a first sub-wavelength structure arranged between the first reflecting member and the first lower electrode, and a second sub-wavelength structure arranged between the second reflecting member and the second lower electrode The first sub-wavelength structure and the second sub-wavelength structure have effective refractive indices different from each other.
    Type: Application
    Filed: November 11, 2025
    Publication date: May 14, 2026
    Inventors: KOSUKE ASANO, TETSUYA KIMURA
  • Publication number: 20260136854
    Abstract: A method of processing a substrate having a first surface with an outer peripheral portion lower than a central portion and forming a second surface flatter than the first surface is provided. The method includes forming a planarization film on at least the outer peripheral portion by placing a curable composition on the substrate, bringing a superstrate into contact with the curable composition, and curing the curable composition, and executing CMP before or after the forming. The second surface is formed through the forming and the executing the CMP.
    Type: Application
    Filed: November 5, 2025
    Publication date: May 14, 2026
    Inventors: TETSUYA KIMURA, KOSUKE ASANO, HIROSHI KUROSAWA
  • Publication number: 20250294910
    Abstract: A semiconductor device includes a plurality of wirings each having a damascene structure on a semiconductor layer, wherein the plurality of wirings includes a first wiring and a second wiring adjacent to each other, wherein the first wiring includes, along a direction in which the first wiring extends, a first portion, a second portion, and a third portion located between the first portion and the second portion, and wherein a width of the third portion is larger than each of a width of the first portion and a width of the second portion.
    Type: Application
    Filed: May 30, 2025
    Publication date: September 18, 2025
    Inventors: Junya Tamaki, Takafumi Miki, Ryo Yoshida, Atsushi Kanome, Kosuke Asano, Takehiro Toyoda, Masaki Kurihara
  • Patent number: 12349495
    Abstract: A semiconductor device includes a plurality of wirings each having a damascene structure on a semiconductor layer, wherein the plurality of wirings includes a first wiring and a second wiring adjacent to each other, wherein the first wiring includes, along a direction in which the first wiring extends, a first portion, a second portion, and a third portion located between the first portion and the second portion, and wherein a width of the third portion is larger than each of a width of the first portion and a width of the second portion.
    Type: Grant
    Filed: February 16, 2021
    Date of Patent: July 1, 2025
    Assignee: Canon Kabushiki Kaisha
    Inventors: Junya Tamaki, Takafumi Miki, Ryo Yoshida, Atsushi Kanome, Kosuke Asano, Takehiro Toyoda, Masaki Kurihara
  • Publication number: 20250100460
    Abstract: An in-vehicle system includes: an in-vehicle device that includes a device main unit with a panel provided on a front surface thereof; a cluster panel that is arranged on the panel; a positioning mechanism which mutually positions the panel and the cluster panel; a vehicle mounting bracket that is fixed to the cluster panel and the device main unit, and that is mounted on a vehicle; and multiple mounting holes that are aligned in a vehicle longitudinal direction in the vehicle mounting bracket and which correspond to screw holes which are provided on a side surface of the device main unit, each of which has a larger diameter than each of screw holes, and a vertical diameter of the mounting hole is formed to be larger as the mounting hole is positioned towards a vehicle front side.
    Type: Application
    Filed: December 9, 2024
    Publication date: March 27, 2025
    Inventors: Kosuke Asano, Yuki Takahashi
  • Patent number: 11686688
    Abstract: An inspection apparatus inspecting a wafer on which a plurality of patterns are formed by a plurality of exposure shots, the inspection apparatus comprising: acquisition unit configured to acquire first information representing a positional relation between an inspection mark included in a pattern formed by a first exposure shot and an inspection mark included in a pattern formed by a second exposure shot, and second information representing a positional relation between the inspection mark included in the pattern formed by the second exposure shot and an inspection mark included in a pattern formed by a third exposure shot; and derivation unit configured to derive a linear component of an error caused by a reticle, and a linear component of an error caused by a position of a wafer, on the basis of the first information and the second information.
    Type: Grant
    Filed: December 23, 2020
    Date of Patent: June 27, 2023
    Assignee: Canon Kabushiki Kaisha
    Inventors: Kosuke Asano, Hideki Ina
  • Patent number: 11543755
    Abstract: A method of manufacturing a semiconductor device by using an exposure apparatus having a reticle stage and a projection optical system includes a first period in which substrates are exposed by using a first reticle arranged on the reticle stage, a second period in which substrates are exposed by using a second reticle arranged on the reticle stage, and a third period which is between the first and second periods. The method includes changing, in at least part of the third period, the first reticle arranged on the reticle stage to the second reticle, and performing control, in the first and second periods, to adjust temperature distribution of an optical element of the projection optical system so as to reduce change in aberration of the projection optical system. The third period is shorter than the first period.
    Type: Grant
    Filed: March 19, 2021
    Date of Patent: January 3, 2023
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Takehiro Toyoda, Hiroaki Kobayashi, Hideki Ina, Kosuke Asano, Kouki Miyano
  • Publication number: 20210302842
    Abstract: A method of manufacturing a semiconductor device by using an exposure apparatus having a reticle stage and a projection optical system includes a first period in which substrates are exposed by using a first reticle arranged on the reticle stage, a second period in which substrates are exposed by using a second reticle arranged on the reticle stage, and a third period which is between the first and second periods. The method includes changing, in at least part of the third period, the first reticle arranged on the reticle stage to the second reticle, and performing control, in the first and second periods, to adjust temperature distribution of an optical element of the projection optical system so as to reduce change in aberration of the projection optical system. The third period is shorter than the first period.
    Type: Application
    Filed: March 19, 2021
    Publication date: September 30, 2021
    Inventors: Takehiro Toyoda, Hiroaki Kobayashi, Hideki Ina, Kosuke Asano, Kouki Miyano
  • Publication number: 20210265411
    Abstract: A semiconductor device includes a plurality of wirings each having a damascene structure on a semiconductor layer, wherein the plurality of wirings includes a first wiring and a second wiring adjacent to each other, wherein the first wiring includes, along a direction in which the first wiring extends, a first portion, a second portion, and a third portion located between the first portion and the second portion, and wherein a width of the third portion is larger than each of a width of the first portion and a width of the second portion.
    Type: Application
    Filed: February 16, 2021
    Publication date: August 26, 2021
    Inventors: Junya Tamaki, Takafumi Miki, Ryo Yoshida, Atsushi Kanome, Kosuke Asano, Takehiro Toyoda, Masaki Masaki
  • Publication number: 20210199596
    Abstract: An inspection apparatus inspecting a wafer on which a plurality of patterns are formed by a plurality of exposure shots, the inspection apparatus comprising: acquisition unit configured to acquire first information representing a positional relation between an inspection mark included in a pattern formed by a first exposure shot and an inspection mark included in a pattern formed by a second exposure shot, and second information representing a positional relation between the inspection mark included in the pattern formed by the second exposure shot and an inspection mark included in a pattern formed by a third exposure shot; and derivation unit configured to derive a linear component of an error caused by a reticle, and a linear component of an error caused by a position of a wafer, on the basis of the first information and the second information.
    Type: Application
    Filed: December 23, 2020
    Publication date: July 1, 2021
    Inventors: Kosuke Asano, Hideki Ina, Yoshiyuki Nakagawa, Junya Tamaki, Takehiro Toyoda, Tomoyuki Tezuka, Yasushi Ohta, Masao Ishioka, Yasushi Matsuno
  • Patent number: 10319765
    Abstract: An imaging device includes a pixel region in which a plurality of pixels, each including a photoelectric converter, are arranged, including an effective pixel region, an optical black region covered with a light-shielding film, and a dummy pixel region arranged between the effective pixel region and the optical black region. The pixels arranged in at least the effective pixel region and the optical black region among the plurality of the pixels each include an optical waveguide arranged above the photoelectric converter. The pixels including the optical waveguides are arranged between the effective pixel region and the optical black region so as to be spaced apart from each other by at least a one-pixel pitch.
    Type: Grant
    Filed: June 14, 2017
    Date of Patent: June 11, 2019
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Taro Kato, Akira Okita, Takehito Okabe, Takeru Ohya, Kosuke Asano, Koichiro Iwata, Seiichirou Sakai
  • Publication number: 20180006071
    Abstract: An imaging device includes a pixel region in which a plurality of pixels, each including a photoelectric converter, are arranged, including an effective pixel region, an optical black region covered with a light-shielding film, and a dummy pixel region arranged between the effective pixel region and the optical black region. The pixels arranged in at least the effective pixel region and the optical black region among the plurality of the pixels each include an optical waveguide arranged above the photoelectric converter. The pixels including the optical waveguides are arranged between the effective pixel region and the optical black region so as to be spaced apart from each other by at least a one-pixel pitch.
    Type: Application
    Filed: June 14, 2017
    Publication date: January 4, 2018
    Inventors: Taro Kato, Akira Okita, Takehito Okabe, Takeru Ohya, Kosuke Asano, Koichiro Iwata, Seiichirou Sakai
  • Patent number: 9171107
    Abstract: A calculating method for calculating structural data of a two-level diffractive optical element configured to form a set of light intensity distributions point-symmetrical with respect to an axis on an image plane utilizing an iterative Fourier transform algorithm executed by a computer includes calculating a light intensity distribution and a phase distribution of a plane of the two-level diffractive optical element which has a Fourier transform relationship with the image plane by performing an inverse Fourier transform for a light intensity that is made by removing one of the set of light intensity distributions from the set of light intensity distributions, and calculating structural data of the diffractive optical element based upon the light intensity distribution and the phase distribution which have been calculated.
    Type: Grant
    Filed: March 7, 2013
    Date of Patent: October 27, 2015
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Kosuke Asano
  • Patent number: 9018672
    Abstract: Provided is a semiconductor device including: a semiconductor element arranged on a substrate and having two electrodes; a conductive strip in contact with one of the two electrodes; and a dielectric arranged between another one of the two electrodes and the conductive strip, in which the conductive strip has an opening formed therein, the dielectric has a void formed therein, and the opening and the void are connected to each other.
    Type: Grant
    Filed: November 15, 2013
    Date of Patent: April 28, 2015
    Assignee: Canon Kabushiki Kaisha
    Inventors: Ryota Sekiguchi, Alexis Debray, Yasushi Koyama, Kosuke Asano, Satoshi Yokoyama, Atsushi Kemmochi
  • Publication number: 20140145280
    Abstract: Provided is a semiconductor device including: a semiconductor element arranged on a substrate and having two electrodes; a conductive strip in contact with one of the two electrodes; and a dielectric arranged between another one of the two electrodes and the conductive strip, in which the conductive strip has an opening formed therein, the dielectric has a void formed therein, and the opening and the void are connected to each other.
    Type: Application
    Filed: November 15, 2013
    Publication date: May 29, 2014
    Applicant: CANON KABUSHIKI KAISHA
    Inventors: Ryota Sekiguchi, Alexis Debray, Yasushi Koyama, Kosuke Asano, Satoshi Yokoyama, Atsushi Kemmochi