Abstract: A correlation matrix calculation unit calculates a correlation matrix Rzx for each data element of the frame data. A blood flow luminance image forming unit forms a blood flow extraction filter Pk,N on the basis of an eigenvalue ?i of a rank equal to or lower than a first threshold rank, the eigenvalue being obtained by singular value decomposition on the correlation matrix Rzx, and an eigenvector wi, wiH corresponding to the eigenvalue ?i and applies the blood flow extraction filter Pk,N to frame data F, therebyto forming a blood flow luminance image Uk,N. A tissue image forming unit forms a tissue image including tissue components on the basis of a signal value of each data element forming the plurality of pieces of the frame data. A blood flow extraction image forming unit subtracts the tissue image from the blood flow luminance image Uk, N, thereby forming a blood flow extraction image Uout.

Abstract: An adeno-associated virus (AAV) vector for inserting a desired nucleic acid into a nucleic acid in a cell, wherein the nucleic acid in the cell comprises a region consisting of a first nucleotide sequence and a region consisting of a second nucleotide sequence in order in a direction from a 5? end to a 3? end, wherein the vector comprises a first gRNA target sequence, a region consisting of a first nucleotide sequence, the desired nucleic acid, a region consisting of a second nucleotide sequence, a second gRNA target sequence, a cell-specific promoter, a sequence encoding a Cas9 nuclease, an RNA polymerase III promoter, a sequence encoding a first gRNA recognizing the first gRNA target sequence and a sequence encoding a second gRNA recognizing the second gRNA target sequence, wherein the vector yields a nucleic acid fragment comprising a region consisting of a first nucleotide sequence, the desired nucleic acid and the region consisting of the second nucleotide sequence by the Cas9 nuclease, wherein a first n

Abstract: Provided are an attractant for bone marrow stem cells containing at least one of cinnamtannin B1 and pentagalloylglucose, and a method for attracting bone marrow stem cells in which bone marrow stem cells are attracted by the attractant.

Abstract: Provided are an attractant for bone marrow stem cells containing at least one of cinnamtannin B1 and pentagalloylglucose, and a method for attracting bone marrow stem cells in which bone marrow stem cells are attracted by the attractant.

Abstract: Disclosed herein is a power supply adapter for supplying DC power to a broadcast receiver that processes a broadcast signal. The power supply adapter includes: a converter configured to generate the DC power from AC power; a broadcast signal reception section configured to receive the broadcast signal; a mixer configured to mix the broadcast signal received by the broadcast signal reception section with an output from the converter; and a supply section configured to supply an output from the mixer to the broadcast receiver.

Abstract: Disclosed herein is a power supply adapter for supplying DC power to a broadcast receiver that processes a broadcast signal. The power supply adapter includes: a converter configured to generate the DC power from AC power; a broadcast signal reception section configured to receive the broadcast signal; a mixer configured to mix the broadcast signal received by the broadcast signal reception section with an output from the converter; and a supply section configured to supply an output from the mixer to the broadcast receiver.

Abstract: The present invention relates to a receiver capable of carrying out waveform detection without utilizing a SAW filter.

Abstract: Phase locked loop (PLL) detection circuit that can improve the stability of operation, avoid occurrence of an erroneous operation, and perform PLL lock judgment correctly. Whether a PLL circuit that consists of a phase comparator, a low-pass filter, and a VCO is in a lock state is judged based on a phase error signal in the PLL circuit. The level of the phase error signal is compared with two threshold values, VRL and VRH. When the phase error signal is somewhere between VRL and VRH, a judgment is made that the PLL circuit is in a lock state. A judgment that the PLL circuit is out of a lock state is made in the other cases. This makes it possible to output a correct and stable PLL lock judgment signal.

Abstract: A high impedance circuit capable of operating at a low voltage without narrowing the dynamic range is provided, which includes a first and a second transistors forming differential-pair type circuit, a third and fourth transistors, a pair of collector resistance elements, a resistance element and a pair of current source circuits. The third and the fourth transistors serve as emitter follower circuits which also functions as a DC shift with respect to the differential-pair type circuit, as well as buffer circuits for heightening an input impedance of the first and the second transistors looked from the base side of the third and the fourth transistors. The current flowing in the resistance element is made current-fedback with respect to the resistance elements by the third and the fourth transistors. The input impedance is determined as Z1=V1/ i3=(R1×R2)/(R1−R2), and when R1=R2, the high impedance circuit becomes infinite impedance.

Abstract: A high impedance circuit capable of operating at a low voltage without narrowing the dynamic range is provided, which includes a first and a second transistors forming differential-pair type circuit, a third and fourth transistors, a pair of collector resistance elements, a resistance element and a pair of current source circuits. The third and the fourth transistors serve as emitter follower circuits which also functions as a DC shift with respect to the differential-pair type circuit, as well as buffer circuits for heightening an input impedance of the first and the second transistors looked from the base side of the third and the fourth transistors. The current flowing in the resistance element is made current-fedback with respect to the resistance elements by the third and the fourth transistors. The input impedance is determined as Z1=V1/i3=(R1.times.R2)/(R1-R2), and when R1=R2, the high impedance circuit becomes infinite impedance.

Abstract: An impedance conversion circuit for the use with a video apparatus, an audio apparatus, or a communication apparatus is provided. The impedance conversion circuit can be used at a frequency higher than that conventionally used and is suitable for formation as an integrated circuit. A video apparatus using this impedance conversion circuit, and the like are also proposed. Driving current is supplied to first and second terminals of an impedance circuit in accordance with voltages of first and second input terminals, respectively, and current is made to flow out of the second and first output terminals in accordance with the first and second terminal voltages of the impedance circuit, respectively.

Abstract: An amplifier circuit in which a differential pair of transistors (1a), (1b) is provided. An impedance (2) of a value 2.Z.sub.e is connected in series between the emitters of the transistors (1a), (1b) and these emitters are grounded by way of current sources (3a), (3b) respectively. Input signal sources (4a), (4b) of voltage values.+-.V.sub.IN are connected to the bases of the transistors (1a), (1b) by way of the base-emitter paths of the transistors (5a), (5b) which form a buffer circuit (10). The emitters of the transistors (5a), (5b) are in turn grounded by way of current sources (6a), (6b) respectively. Further, the collectors of each of the transistors (1a), (1b) are connected to the base of the other transistors by way of the base-emitter paths of the transistors (5a), (5b) respectively.

Abstract: A two-terminal paired circuit is disclosed which comprises two sets of differential pairs wherein a first set of the differential pair includes two transistors collectors of which are connected to a pair of input terminals and to a bias circuit serving also as a DC shift, bases of which are connected to the bias circuit to apply a voltage feedback from the collectors to the bases and emitters of which are connected to a constant current source and have an impedance element connected therebetween, a second set of the differential pair includes two transistors collectors of which are connected to a pair of output terminals and to a bias circuit serving also as a DC shift, bases of which are connected to the bias circuit to apply a voltage feedback from the collectors to the bases and emitters of which are connected to a constant current source and have an impedance element connected therebetween, and the voltage feedbacks together with the two sets of differential pairs are applied symmetrical with respect to l

Abstract: A high-performance voltage controlled oscillator without use of variable capacitance (varicap) diodes which is easy in fabrication in an semiconductor IC form. The voltage controlled oscillator includes:a differential amplifier having a differential pair of transistors (Q.sub.1, Q.sub.2); an LC resonance circuit having a coil (L.sub.0) and a capacitor (C.sub.0); a phase shift circuit for receiving a differential output of the differential amplifier via a buffer of transistors (Q.sub.3, Q.sub.4) and for providing its output for the differential amplifier in a positive feedback mode; and a current control circuit for variably controlling an operating current (Ie) of the phase shift circuit according to a controlled voltage applied from a circuit other than those in the voltage controlled oscillator.

Abstract: A control system for an electronic apparatus, such as a television receiver, having a control circuit with a control program in an internal memory sequentially communicates over an internal bus within predetermined intervals, such as within the vertical blanking interval of the television signal, with a plurality of controllable circuits in the television receiver, and the control circuit operates to select and communicate with a specific, selected one of the controllable circuits first, in each predetermined interval, with the remainder of the controllable circuits being subsequently communicated with in the remaining portion of the vertical blanking interval.

Abstract: A system for controlling electronic apparatus, such as a television receiver, which employs a control circuit having a control program in a read only memory to sequentially communicate over an internal system bus in a predetermined interval with a plurality of controllable, operational circuit blocks forming the electronic apparatus, in which the control circuit selects a specific circuit block for data transfer upon a request signal. In one embodiment, a request signal is transmitted prior to a vertical blanking interval in a television signal and in another embodiment, a dedicated line is provided from a selected controllable unit to the control unit, whereby the request signal can be transmitted at any time, irrespective of whether data is being transferred at such time.