Patents by Inventor Kosuke Hareyama

Kosuke Hareyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230420404
    Abstract: The present disclosure relates to an imaging element package, a method of manufacturing the same, and an electronic device capable of further improving reliability. An imaging element package includes a solid-state imaging element having a first pad, a substrate on which the solid-state imaging element is mounted, the substrate having a second pad, and a wire wiring that connects the first pad and the second pad. The wire wiring has a ball portion bonded to the first pad in a shape having a thickness equal to or larger than a depth of an opening portion provided for opening the first pad, and a crescent portion provided by pressing an end of the metal wire against the ball portion and bonding the end to the ball portion, and connected to the metal wire with a connection length of a predetermined ratio or more with respect to the metal wire.
    Type: Application
    Filed: November 16, 2021
    Publication date: December 28, 2023
    Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Yuji HARA, Kosuke HAREYAMA
  • Publication number: 20230263060
    Abstract: Provided is a thermoelectric power generation module that uses a thermoelectric power generation element and, for example, improves the efficiency of thermoelectric power generation according to heat generated by a semiconductor component, etc.
    Type: Application
    Filed: June 8, 2021
    Publication date: August 17, 2023
    Inventors: KOSUKE HAREYAMA, CHRISTOPHER WRIGHT, MATTHEW LAWRENSON, BERNADETTE ELLIOTT-BOWMAN, TIMOTHY BEARD
  • Publication number: 20220139979
    Abstract: An improvement in heat radiation efficiency is achieved. A semiconductor device according to the present technology includes a substrate portion on which a semiconductor chip is mounted and in which an external connection terminal for performing electrical connection to the outside is formed on a rear surface on a side opposite to a front surface which is a surface on a side where the semiconductor chip is mounted, an outer wall portion that protrudes toward the front surface side in an outer circumferential portion of the substrate portion, a lid portion which is supported by the outer wall portion and covers the semiconductor chip, and a heat storage member which is disposed at a position further inside than the outer wall portion between the rear surface of the substrate portion and a rear surface of the lid portion.
    Type: Application
    Filed: January 5, 2020
    Publication date: May 5, 2022
    Inventors: TSUYOSHI WATANABE, HIROKAZU NAKAYAMA, HIROYUKI SHIGETA, HITOSHI SHIBUE, HIROTAKA KOBAYASHI, KOSUKE HAREYAMA
  • Publication number: 20210233949
    Abstract: Deformation of a semiconductor chip is to be prevented in a semiconductor device in which a heat releasing plate and a circuit board are disposed. The semiconductor device includes the semiconductor chip, the circuit board, the heat releasing plate, an adhesive member, and a conductive member. The circuit board transmits a signal of the semiconductor chip. The heat releasing plate has the semiconductor chip disposed thereon, and has an opening in a region on the outer side of a semiconductor chip placement region that is a region in which the semiconductor chip is disposed. The adhesive member is disposed in a region on the outer side of the opening on a different surface of the heat releasing plate from the surface on which the semiconductor chip is disposed, and bonds the circuit board and the heat releasing plate to each other. The conductive member connects the semiconductor chip and the circuit board to each other via the opening.
    Type: Application
    Filed: June 21, 2019
    Publication date: July 29, 2021
    Inventors: DAISUKE CHINO, HIROYUKI SHIGETA, SHIGEKAZU ISHII, KOYO HOSOKAWA, HIROHISA YASUKAWA, MITSUHITO KANATAKE, KOSUKE HAREYAMA, YUTAKA OOTAKI, KIYOHISA SAKAI, ATSUSHI TSUKADA, HIROTAKA KOBAYASHI, NINAO SATO, YUKI YAMANE
  • Patent number: 10580816
    Abstract: The present technology relates to a solid-state imaging device capable of preventing defects in the appearance thereof, a camera module, and an electronic apparatus. The solid-state imaging device to be provided includes: a semiconductor substrate having pixels formed therein, the pixels each including a photoelectric conversion element; and on-chip lenses formed above the semiconductor substrate, the on-chip lenses corresponding to the pixels. The area in which the on-chip lenses are formed is extended to a peripheral area outside an imaging area formed with the pixels. The present technology can be applied to solid-state imaging devices, such as CMOS image sensors.
    Type: Grant
    Filed: October 22, 2015
    Date of Patent: March 3, 2020
    Assignee: SONY CORPORATION
    Inventor: Kosuke Hareyama
  • Patent number: 10332826
    Abstract: A semiconductor device including a plurality of solder balls on a surface the semiconductor device, and a retaining body associated with a first solder ball of the plurality of solder balls, separating the first solder ball from at least a second solder ball of the plurality of solder balls. The retaining body includes a conductive portion and an insulating portion configured to cover the conductive portion. Also, a method of manufacturing a semiconductor device, including acts of forming a plurality of retaining bodies on a surface of a wiring substrate, each retaining body comprising a conductive portion and an insulating portion covering the conductive portion, each retaining body forming an opening section, and forming a solder ball in the opening section formed by each of the retaining bodies.
    Type: Grant
    Filed: February 27, 2014
    Date of Patent: June 25, 2019
    Assignee: Sony Corporation
    Inventors: Kosuke Hareyama, Daisuke Chino, Yuuji Nishitani
  • Patent number: 10187971
    Abstract: A wiring board that includes: insulation layers and wiring layers which are laminated alternately; a component connection pad present on one surface of the wiring board in a lamination direction of the insulation layers and the wiring layers, and to which an electronic component is connected; a circuit connection pad present on another surface of the wiring board in the lamination direction and is connected to a circuit board; and a structure which includes a coaxial structure, wherein each of the wiring layers is connected by a via, and the coaxial structure includes an inner wiring part extending in the lamination direction and an outer wiring part located on a side corresponding to an outer peripheral surface of the inner wiring part through an insulating resin, and the inner wiring part is electrically connected to the component connection pad and the circuit connection pad.
    Type: Grant
    Filed: August 16, 2013
    Date of Patent: January 22, 2019
    Assignee: Sony Corporation
    Inventor: Kosuke Hareyama
  • Patent number: 10008458
    Abstract: The present technology relates to a semiconductor device and a method of manufacturing the semiconductor device capable of realizing impedance control of the semiconductor device. An input/output wiring line 23 and a ground wiring line 22 are such that through glass vias are provided so as to form a strip line structure by blasting or electric discharge machining and thereafter metal films are formed on a surface and a rear surface. It is possible to configure the semiconductor device with the impedance control by adjusting a conductor diameter of the input/output wiring line 23 and an insulating layer thickness between the input/output wiring line 23 and the ground wiring line 22. The present technology may be applied to the semiconductor device.
    Type: Grant
    Filed: June 16, 2015
    Date of Patent: June 26, 2018
    Assignee: SONY CORPORATION
    Inventor: Kosuke Hareyama
  • Publication number: 20170317127
    Abstract: The present technology relates to a solid-state imaging device capable of preventing defects in the appearance thereof, a camera module, and an electronic apparatus. The solid-state imaging device to be provided includes: a semiconductor substrate having pixels formed therein, the pixels each including a photoelectric conversion element; and on-chip lenses formed above the semiconductor substrate, the on-chip lenses corresponding to the pixels. The area in which the on-chip lenses are formed is extended to a peripheral area outside an imaging area formed with the pixels. The present technology can be applied to solid-state imaging devices, such as CMOS image sensors.
    Type: Application
    Filed: October 22, 2015
    Publication date: November 2, 2017
    Inventor: KOSUKE HAREYAMA
  • Publication number: 20170154860
    Abstract: The present technology relates to a semiconductor device and a method of manufacturing the semiconductor device capable of realizing impedance control of the semiconductor device. An input/output wiring line 23 and a ground wiring line 22 are such that through glass vias are provided so as to form a strip line structure by blasting or electric discharge machining and thereafter metal films are formed on a surface and a rear surface. It is possible to configure the semiconductor device with the impedance control by adjusting a conductor diameter of the input/output wiring line 23 and an insulating layer thickness between the input/output wiring line 23 and the ground wiring line 22. The present technology may be applied to the semiconductor device.
    Type: Application
    Filed: June 16, 2015
    Publication date: June 1, 2017
    Inventor: KOSUKE HAREYAMA
  • Publication number: 20150380347
    Abstract: A semiconductor device including a plurality of solder balls on a surface the semiconductor device, and a retaining body associated with a first solder ball of the plurality of solder balls, separating the first solder ball from at least a second solder ball of the plurality of solder balls. The retaining body includes a conductive portion and an insulating portion configured to cover the conductive portion. Also, a method of manufacturing a semiconductor device, including acts of forming a plurality of retaining bodies on a surface of a wiring substrate, each retaining body comprising a conductive portion and an insulating portion covering the conductive portion, each retaining body forming an opening section, and forming a solder ball in the opening section formed by each of the retaining bodies.
    Type: Application
    Filed: February 27, 2014
    Publication date: December 31, 2015
    Applicant: SONY CORPORATION
    Inventors: Kosuke Hareyama, Daisuke Chino, Yuuji Nishitani
  • Publication number: 20150230329
    Abstract: The present technology relates to a wiring board and a method of manufacturing a wiring board which improve the accuracy of control related to an impedance and mitigate a transmission loss of a signal.
    Type: Application
    Filed: August 16, 2013
    Publication date: August 13, 2015
    Applicant: Sony Corporation
    Inventor: Kosuke Hareyama