Patents by Inventor Kosuke Hatsuda
Kosuke Hatsuda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20120060066Abstract: This disclosure concerns a memory including: a first memory region including memory groups including a plurality of memory cells, addresses being respectively allocated for the memory groups, the memory groups respectively being units of data erase operations; a second memory region temporarily storing therein data read from the first memory region or temporarily storing therein data to be written to the first memory region; a read counter storing therein a data read count for each memory group; an error-correcting circuit calculating an error bit count of the read data; and a controller performing a refresh operation, in which the read data stored in one of the memory groups is temporarily stored in the second memory region and is written back the read data to the same memory group, when the error bit count exceeds a first threshold or when the data read count exceeds a second threshold.Type: ApplicationFiled: November 16, 2011Publication date: March 8, 2012Applicant: Kabushiki Kaisha ToshibaInventors: Yasushi Nagadomi, Daisaburo Takashima, Kosuke Hatsuda
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Patent number: 8108593Abstract: A system includes: a first input buffer that functions as an input buffer for a third storing area; and a second input buffer that functions as an input buffer for the third storing area and that separately stores data with a high update frequency for the third storing area. In the system, a plurality of data written in a first storing area or a second storing area are flushed to the first input buffer in units of logical blocks. Also, a plurality of data written in the first input buffer are relocated to the third storing area in units of logical blocks.Type: GrantFiled: March 2, 2009Date of Patent: January 31, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Junji Yano, Hidenori Matsuzaki, Kosuke Hatsuda, Wataru Okamoto, Ryoichi Kato
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Patent number: 8108594Abstract: To provide a memory system that can surely restore management information even when a program error occurs during data writing. After “log writing (1)” for a pre-log, when a program error occurs when data writing is being performed (a data writing error), the memory system performs the data writing again without acquiring a pre-log corresponding to data rewriting processing. After finishing the data writing, the memory system acquires, without generating a post-log, a snapshot instead of the post-log and finishes the processing.Type: GrantFiled: February 10, 2009Date of Patent: January 31, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Junji Yano, Hidenori Matsuzaki, Kosuke Hatsuda, Hiroki Matsudaira
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Publication number: 20110307667Abstract: A memory system according to an embodiment of the present invention comprises: a first management table that manages addresses concerning the data written in a first storing area; and a second management table that manages, in an address unit of a second management unit, information indicating temporal order of the data stored in the first storing area and manages, for each of addresses in a second management unit, number-of-valid-data information indicating a number of data in the first management unit included in the addresses in the second management unit.Type: ApplicationFiled: February 10, 2009Publication date: December 15, 2011Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Junji Yano, Kosuke Hatsuda, Hidenori Matsuzaki, Ryoichi Kato
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Patent number: 8078923Abstract: This disclosure concerns a memory including: a first memory region including memory groups including a plurality of memory cells, addresses being respectively allocated for the memory groups, the memory groups respectively being units of data erase operations; a second memory region temporarily storing therein data read from the first memory region or temporarily storing therein data to be written to the first memory region; a read counter storing therein a data read count for each memory group; an error-correcting circuit calculating an error bit count of the read data; and a controller performing a refresh operation, in which the read data stored in one of the memory groups is temporarily stored in the second memory region and is written back the read data to the same memory group, when the error bit count exceeds a first threshold or when the data read count exceeds a second threshold.Type: GrantFiled: September 30, 2008Date of Patent: December 13, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Yasushi Nagadomi, Daisaburo Takashima, Kosuke Hatsuda
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Publication number: 20110264859Abstract: A memory system according to an embodiment of the present invention comprises: a data managing unit 120 is divided into a DRAM-layer managing unit 120a, a logical-NAND-layer managing unit 120b, and a physical-NAND-layer managing unit 120c to independently perform management of a DRAM layer, a logical NAND layer, and a physical NAND layer using the respective managing units to thereby perform efficient block management.Type: ApplicationFiled: February 10, 2009Publication date: October 27, 2011Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Junji Yano, Kosuke Hatsuda, Hidenori Matsuzaki
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Publication number: 20110231598Abstract: According to one embodiment, a memory system includes a first memory that is nonvolatile, a second memory, and a controller that performs data transfer between a host device and the first memory by using the second memory. The controller caches data of each write command transmitted from the host device in the second memory, and performs a first transfer of transferring the data of each write command, which is cached in the second memory, to the first memory while leaving a beginning portion at a predetermined timing.Type: ApplicationFiled: July 13, 2010Publication date: September 22, 2011Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Kosuke HATSUDA
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Publication number: 20110231734Abstract: A memory system includes a controlling unit that configured to control data transfer between the first and the second memory. The controlling unit executes copy processing for, after reading out data stored in a first page of the second memory to the first memory, writing the data in a second page of the second memory, determines, when executing the copy processing, whether the error correction processing for the data read out from the first page is successful, stores, when the error correction processing is successful, corrected data in the first memory and writes the corrected data in the second page, and reads out, when the error correction processing is unsuccessful, the data from the first page to the first memory and writes the data not subjected to the error correction processing in the second page.Type: ApplicationFiled: June 3, 2011Publication date: September 22, 2011Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Junji YANO, Hidenori Matsuzaki, Kosuke Hatsuda, Hiroki Matsudaira
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Publication number: 20110185108Abstract: A memory system includes a volatile first storing unit, a nonvolatile second storing unit in which a plurality of memory cells that can store multi-value data are arranged, the memory cells having a plurality of pages, and a controller that performs data transfer between a host apparatus and the second storing unit via the first storing unit. The controller includes a save processing unit that backs up, when, before data is written in the second storing unit in a write-once manner, data is written in a lower order page of a memory cell same as that of a page in which the data is written, the data of the lower order page and a broken-information-restoration processing unit that restores, when the data in the lower order page is broken, the broken data using the backed-up data.Type: ApplicationFiled: February 10, 2009Publication date: July 28, 2011Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Junji Yano, Hidenori Matsuzaki, Kosuke Hatsuda
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Publication number: 20110185105Abstract: A memory system in which speed of processing for searching through management tables is increased by providing a forward lookup table for searching for, respectively in track and cluster units, from a logical address, a storage device position where data corresponds to the logical address, and a reverse lookup table for searching for, from a position of the storage device, a logical address stored in the position. These forward and reverse lookup tables are linked.Type: ApplicationFiled: February 10, 2009Publication date: July 28, 2011Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Junji Yano, Kosuke Hatsuda, Hidenori Matsuzaki
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Publication number: 20110185107Abstract: A memory system includes a volatile first storing unit, a nonvolatile second storing unit, and a controller. The controller performs data transfer, stores management information including a storage position of the data stored in the second storing unit into the first storing unit, and performs data management while updating the management information. The second storing unit has a management information storage area for storing management information storage information including management information in a latest state and a storage position of the management information. The storage position information is read by the controller during a startup operation of the memory system and includes a second pointer indicating a storage position of management information in a latest state in the management information storage area and a first pointer indicating a storage position of the second pointer.Type: ApplicationFiled: February 10, 2009Publication date: July 28, 2011Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Junji Yano, Hidenori Matsuzaki, Kosuke Hatsuda, Shigehiro Asano, Shinichi Kanno, Toshikatsu Hida
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Publication number: 20110185106Abstract: A memory system includes a management-information restoring unit. The management-information restoring unit determines whether a short break has occurred referring to a pre-log or a post-log in a NAND memory. The management-information restoring unit determines that a short break has occurred when the pre-log or the post-log is present in the NAND memory. In that case, the management-information restoring unit determines timing of occurrence of the short break, and, after selecting a pre-log or a post-log used for restoration, performs restoration of the management information reflecting these logs on a snapshot. Thereafter, the management-information restoring unit applies recovery processing to all write-once blocks in the NAND memory, takes the snapshot again, and opens the snapshot and the logs in the past.Type: ApplicationFiled: February 10, 2009Publication date: July 28, 2011Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Junji Yano, Hidenori Matsuzaki, Kosuke Hatsuda
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Publication number: 20110099349Abstract: A controller executes first processing for writing a plurality of data in a sector unit in the first storing area; second processing for flushing the data stored in the first storing area to the first input buffer in a first management unit twice or larger natural number times as large as the sector unit; third processing for flushing the data stored in the first storing area to the second input buffer in a second management unit twice or larger natural number times as large as the first management unit; fourth processing for relocating a logical block in which all pages are written in the first input buffer to the second storing area; fifth processing for relocating a logical block in which all pages are written in the second input buffer to the third storing area; and sixth processing for flushing a plurality of data stored in the second storing area to the second input buffer in the second management unit.Type: ApplicationFiled: January 4, 2011Publication date: April 28, 2011Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Junji Yano, Hidenori Matsuzaki, Kosuke Hatsuda
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Patent number: 7904640Abstract: A controller executes first processing for writing a plurality of data in a sector unit in the first storing area; second processing for flushing the data stored in the first storing area to the first input buffer in a first management unit twice or larger natural number times as large as the sector unit; third processing for flushing the data stored in the first storing area to the second input buffer in a second management unit twice or larger natural number times as large as the first management unit; fourth processing for relocating a logical block in which all pages are written in the first input buffer to the second storing area; fifth processing for relocating a logical block in which all pages are written in the second input buffer to the third storing area; and sixth processing for flushing a plurality of data stored in the second storing area to the second input buffer in the second management unit.Type: GrantFiled: September 22, 2008Date of Patent: March 8, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Junji Yano, Hidenori Matsuzaki, Kosuke Hatsuda
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Publication number: 20110055462Abstract: According to one embodiment, a memory system includes a nonvolatile first memory, a nonvolatile second memory, a data-copy processing unit and a data invalidation processing unit. The first memory has a storage capacity for n (n?2) pages per word line. The nonvolatile second memory temporarily stores user data write-requested from a host apparatus. The data-copy processing unit executes data copy processing including reading out, in page units, the user data stored in the second memory and sequentially writing the read-out user data in page units in the first memory. The data invalidation processing unit selects, after the execution of the data copy processing, based on whether the memory cell group per word line stores user data for n pages, user data requiring backup out of the user data subjected to the data copy processing and leaves the selected user data in the second memory as backup data.Type: ApplicationFiled: August 20, 2010Publication date: March 3, 2011Applicant: Kabushiki Kaisha ToshibaInventors: Kosuke HATSUDA, Daisaburo Takashima
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Publication number: 20110022784Abstract: A memory system according to an embodiment of the present invention comprises: a memory amount required for management table creation is reduced by adopting a nonvolatile semiconductor memory including a plurality of parallel operation elements respectively having a plurality of physical blocks as units of data erasing and a controller that can drive the parallel operation elements in parallel and has a number-of-times-of-erasing managing unit that manages the number of times of erasing in logical block units associated with a plurality of physical blocks driven in parallel.Type: ApplicationFiled: February 10, 2009Publication date: January 27, 2011Inventors: Junji Yano, Kosuke Hatsuda, Hidenori Matsuzaki, Toshikatsu Hida
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Publication number: 20100312948Abstract: A memory system includes a DRAM 20 that performs writing and readout in a unit equal to or smaller than a cluster, a NAND memory 10 that performs writing and readout in a page unit, and a management table group in which management information including storage locations of data stored in the DRAM 20 and the NAND memory 10 is stored. When a readout request is received from the outside, a data managing unit 120 notifies, when an unwritten logical address area is present in a storage area of the NAND memory to which a logical address area requested to be read out is mapped, fixed data stored in the DRAM 20 to the outside in association with the logical address area.Type: ApplicationFiled: February 10, 2009Publication date: December 9, 2010Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Junji Yano, Hidenori Matsuzaki, Kosuke Hatsuda
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Publication number: 20100281204Abstract: A memory system includes a WC 21 from which data is read out and to which data is written in sector units by a host apparatus, an FS 12 from which data is read out and to which data is written in page units, an MS 11 from which data is read out and to which data written in track units, an FSIB 12a functioning as an input buffer for the FS 12, and an MSIB 11a functioning as an input buffer to the MS 11. An FSBB 12ac that has a capacity equal to or larger than a storage capacity of the WC 21 and stores data written in the WC 21 is provided in the FSIB12a. A data managing unit 120 that manages the respective storing units suspends, when it is judged that one kind of processing performed among the storing units exceeds predetermined time, the processing judged as exceeding the predetermined time and controls the data written in the WC 21 to be saved in the FSBB 12ac.Type: ApplicationFiled: September 22, 2008Publication date: November 4, 2010Applicant: Kabushiki Kaisha ToshibaInventors: Junji Yano, Hidenori Matsuzaki, Kosuke Hatsuda
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Publication number: 20100274950Abstract: A controller executes first processing for writing a plurality of data in a sector unit in the first storing area; second processing for flushing the data stored in the first storing area to the first input buffer in a first management unit twice or larger natural number times as large as the sector unit; third processing for flushing the data stored in the first storing area to the second input buffer in a second management unit twice or larger natural number times as large as the first management unit; fourth processing for relocating a logical block in which all pages are written in the first input buffer to the second storing area; fifth processing for relocating a logical block in which all pages are written in the second input buffer to the third storing area; and sixth processing for flushing a plurality of data stored in the second storing area to the second input buffer in the second management unit.Type: ApplicationFiled: September 22, 2008Publication date: October 28, 2010Applicant: Kabushiki Kaisha ToshibaInventors: Junji Yano, Hidenori Matsuzaki, Kosuke Hatsuda
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Patent number: 7778078Abstract: A memory system includes: a flash memory that stores data; a memory that stores a read count table that indicates the number of times of data read from the flash memory; and a controller that performs: reading out the data from the flash memory; updating the read count table when the controller performs reading out the data from the flash memory; and refreshing the flash memory based on the read count table.Type: GrantFiled: January 24, 2008Date of Patent: August 17, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Yasushi Nagadomi, Daisaburo Takashima, Kosuke Hatsuda