Patents by Inventor Kosuke IMAI

Kosuke IMAI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20260072691
    Abstract: A central processing unit (CPU) 20 of a micro controller unit (MCU) 10 (information processing apparatus) sequentially executes a first-partial program (Block J) and a second-partial program (Block K). The first-partial program causes the CPU 20 to perform redundancy execution of the first unique process associated with the first-partial program twice or more (Steps S202-S208 and S212-S218). Then, the first-partial program causes the CPU 20 to record each piece of output data output for each of first unique processes (unique processes J_0 and J_1) in each of the first data regions (data regions D0j and D1j) pre-allocated to each piece of output data, and permit execution of the second-partial program subsequently to the first-partial program (Step S238) when pieces of output data of the first unique process or digest values of the output data recorded in first data regions match (Steps S220 and S228).
    Type: Application
    Filed: July 21, 2025
    Publication date: March 12, 2026
    Applicants: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Mikio HASHIMOTO, Koichi ETO, Yasuhiro FUKUJU, Koji KITAYAMA, Hirohisa KUSANO, Kosuke IMAI
  • Publication number: 20260064853
    Abstract: A control device 10 includes an MCU 20 including a CPU 22, a system bus 26, storage 28, and an address translator 24 translating an address in the CPU address space of the CPU 22 to and from an address in the system bus address space of the system bus 26 according to the translation rule set in the special function register 24A. The MCU 20 starts up in the limitation-release mode in which all addresses in the CPU address space are available, and switches to the limitation mode in which only some of the addresses in the CPU address space are available when a predetermined condition is satisfied after the start-up. For the special function register 24A, the translation rule is settable and readable in the limitation release mode, and the translation rule is neither settable nor readable in the limitation mode.
    Type: Application
    Filed: July 30, 2025
    Publication date: March 5, 2026
    Applicants: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Koji KITAYAMA, Mikio HASHIMOTO, Shinnosuke YAMAOKA, Hirohisa KUSANO, Kosuke IMAI
  • Publication number: 20130063599
    Abstract: A vehicle driving support processing device, including a first data acquisition unit that acquires left rear image data, a second data acquisition unit that acquires right rear image data, and a lane departure detection unit having a lane departure detection state and a lane departure detection inhibition state, wherein the lane departure detection unit in the lane departure detection state estimates a first distance between a left-side boundary and the vehicle based on the left rear image data, estimates a second distance between a right-side boundary and the vehicle based on the right rear image data, and performs a signal generation operation to generate a signal for a warning or for controlling a steering gear or a braking device, and for transmitting a signal to other vehicles.
    Type: Application
    Filed: September 14, 2012
    Publication date: March 14, 2013
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kosuke IMAI, Kenji FURUKAWA, Nobuyuki OZAKI